DRAM ECC Flag-Bit Tracking for Reduced-Power Refresh
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Solution Overview
Problem
Existing memory systems face challenges in reducing power consumption during refresh operations in DRAM devices, as current error correction techniques require significant time and power to generate and store syndromes, leading to increased latency and power consumption, especially when entering or exiting reduced power refresh modes.
Innovation Solution
An error checking and correction method that uses a flag bit to determine if data has been modified since the last refresh, allowing for the generation and storage of new syndromes only when necessary, thereby reducing the need for frequent syndrome generation and storage, and enabling efficient data integrity checks and corrections during reduced power refresh modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction techniques are used to ensure data integrity during refresh operations, then data reliability is improved, but power consumption and latency increase due to frequent syndrome generation and storage
Solution Approach 1:
The patent applies preliminary action by setting a flag bit to indicate when data has been modified, so that syndrome generation is only performed when necessary. This allows the system to prepare in advance by tracking modifications rather than continuously generating syndromes, reducing unnecessary power consumption while maintaining data integrity.
Solution Approach 2:
The patent uses partial action by performing syndrome generation only for data blocks that have been modified (indicated by the flag bit), rather than generating syndromes for all data blocks during every refresh operation. This selective approach reduces the frequency of syndrome generation and storage operations, thereby lowering power consumption while still ensuring data integrity for modified blocks.
2Reliability
If syndrome generation and storage is performed frequently to correct data errors, then data reliability is improved, but read latency increases
Solution Approach 1:
The flag bit serves as a preliminary indicator that tracks data modifications, allowing the system to determine in advance whether syndrome generation is needed. This eliminates the need for frequent syndrome generation during read operations, thereby reducing read latency while maintaining data correctness.
Solution Approach 2:
The patent performs syndrome generation only partially, specifically only for data blocks where the flag bit indicates modification has occurred. This selective syndrome generation reduces the time required for error correction operations, thereby reducing read latency while still ensuring data correctness for modified blocks.
3Use of energy by moving object
If refresh rate is reduced to lower power consumption, then energy efficiency is improved, but data loss risk increases
Solution Approach 1:
The flag bit provides preliminary tracking of data modifications, allowing the system to identify which data blocks require syndrome generation even at reduced refresh rates. This enables the system to maintain data retention for modified blocks while operating at lower power consumption levels.
Solution Approach 2:
The patent applies partial action by generating syndromes only for modified data blocks (identified by the flag bit) rather than performing full refresh operations on all data blocks. This selective approach allows the system to reduce the overall refresh rate and power consumption while still ensuring data retention for blocks that have been modified and require error correction.
Data Source
AI summary
A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data.