DRAM Tag-Integrated Cache for Lower SCM Access Latency
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Solution Overview
Problem
Existing DRAM systems face challenges in scaling and latency when combined with storage class memory (SCM) due to the longer latency and limited endurance of SCM, leading to inefficiencies in hybrid memory systems.
Innovation Solution
Modifying DRAM architecture to enable tag storage and comparison on the DRAM, allowing it to function as a multiway set associative cache, reducing latency and power overhead by performing tag matching within the DRAM rather than external circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If SCM is used to increase memory capacity, then storage capacity is improved, but access latency increases
Solution Approach 1:
The memory system is segmented into two distinct parts: DRAM cache for fast access and SCM for large capacity storage. The DRAM cache holds frequently accessed data and tags, while SCM provides bulk storage. This segmentation allows the system to leverage the speed of DRAM for critical operations while maintaining the high capacity of SCM.
Solution Approach 2:
The DRAM cache acts as an intermediary between the processor and SCM. By storing copies of SCM data in DRAM along with associated tags, the system can serve requests from the fast DRAM cache when possible, reducing accesses to slow SCM. The tag storage within DRAM enables efficient cache hit/miss determination without external circuitry.
2Adaptability or versatility
If external tag matching circuits are used, then cache functionality is achieved, but device complexity and power consumption increase
Solution Approach 1:
The tag storage and data storage are merged into the same DRAM array structure. Tags are stored in dedicated rows within the DRAM device, eliminating the need for separate external tag matching circuits. This integration reduces overall system complexity while maintaining full cache functionality.
Solution Approach 2:
The DRAM device performs multiple functions: it stores both data and tags, performs tag matching operations, and provides cache functionality. By making the DRAM device universal and multi-functional, the system eliminates dedicated external circuits for tag matching, reducing device complexity and power consumption.
3Productivity
If DRAM is modified for tag storage, then cache efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The invention changes the operational parameters of standard DRAM devices by repurposing existing redundant rows for tag storage and modifying the control logic to perform tag matching. This approach allows cache functionality to be achieved through parameter changes rather than fundamental structural modifications, easing manufacturing.
Data Source
AI summary
Disclosed is a dynamic random access memory (DRAM) that includes a plurality of data rows and a plurality of tag rows. The DRAM includes a communication interface to receive a first group of address bits. The DRAM includes one or more comparators to generate a tag match indication and one or more set bits based on the first group of address bits and a first group of tag information bits from the plurality of tag rows. The one or more comparators are further to combine, based on the tag match indication, the one or more set bits and the first group of address bits to generate a second group of address bits.