DRAM Tag Mapping for Refresh-Tolerant Memory Access
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Solution Overview
Problem
Existing DRAM access operations are inefficient due to the need to accommodate refresh schedules, leading to decreased performance and increased manufacturing costs with multiple I/O lines, and subsequent requests for data when previous requests fail due to memory operations.
Innovation Solution
Implementing a tag identifier that associates multiple memory locations with a single identifier, allowing efficient data retrieval and accommodating refresh schedules without additional commands or addresses, thereby optimizing memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple I/O lines are added to increase data transfer capacity, then data transfer efficiency is improved, but manufacturing cost and device complexity increase
Solution Approach 1:
The existing I/O lines are made multi-functional by enabling them to handle both data transfer operations and refresh operations. The memory controller intelligently multiplexes the use of I/O lines, allowing the same physical lines to serve multiple purposes at different time intervals, thereby achieving improved data transfer efficiency without adding more physical I/O lines.
Solution Approach 2:
The system dynamically allocates I/O line usage based on operational needs. During refresh operations, I/O lines are assigned to refresh tasks, while during data transfer operations, the same lines are assigned to data movement. This dynamic time-multiplexing approach allows the system to adaptively optimize performance without increasing hardware complexity.
2Reliability
If DRAM access operations accommodate refresh schedules, then memory stability is maintained, but access performance decreases
Solution Approach 1:
The system performs refresh operations in advance or in parallel with data access operations where possible. By proactively managing refresh schedules and pre-loading data into buffer regions during refresh cycles, the system ensures that required data is ready when needed, maintaining both memory stability and access performance without forcing sequential execution of refresh and access operations.
Solution Approach 2:
Buffer memory regions are introduced as intermediary storage between the main DRAM array and the output interface. These buffers allow data to be pre-fetched and held during refresh operations, decoupling the refresh timing from the data access timing. This intermediary mechanism enables refresh operations to proceed without blocking subsequent data access performance.
3Reliability
If subsequent requests are sent when previous requests fail, then data retrieval reliability is improved, but access time increases
Solution Approach 1:
The system pre-loads data into buffer regions during refresh operations or idle periods before actual access requests are made. This preliminary action ensures that when data is requested, it is already available in the buffer, eliminating the need for subsequent retry requests and reducing access time while maintaining high retrieval reliability.
Solution Approach 2:
Instead of idle waiting followed by retry requests, the system continuously utilizes buffer memory to pre-fetch and hold data during refresh cycles and idle periods. This continuous useful action ensures that data is ready for immediate access when requested, eliminating gaps and retries, thereby reducing access time while maintaining reliability.
Data Source
AI summary
Systems, methods, and apparatuses are provided for a tag identifier for a memory device. A dynamic random access memory (DRAM) array can be coupled to a controller that is configured to maintain a tag match table indicating correspondence between a respective tag identifier and a respective plurality of DRAM addresses for each of a plurality of tag identifiers, receive a memory access request that includes a particular tag identifier, retrieve the respective plurality of DRAM addresses corresponding to the particular tag identifier from the tag match table, and access memory corresponding to the respective plurality of DRAM addresses.