DRAM Capacitor Through-Hole Etching With Edge-Thinned Film Layers
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Solution Overview
Problem
Miniaturization of dynamic random access memory (DRAM) capacitors leads to shrinkage defects due to non-uniform etching, causing connectivity issues between capacitance structures and reducing device yield.
Innovation Solution
A method involving a stacked film layer structure with a thinner first film layer at the edge of the wafer, achieved through chemical mechanical grinding, to ensure uniform etching and prevent shrinkage defects, where the thickness of the first film layer is reduced more at the edge than at the center, allowing for proper connection of capacitance structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the capacitor geometric size is reduced according to Moore's law, then the storage density is improved, but the etching uniformity deteriorates causing shrinkage defects
Solution Approach 1:
The patent applies local quality by creating a non-uniform first film layer where the thickness varies across the wafer surface. Specifically, the first film layer is thinner at the edge region and thicker at the center region, compensating for the non-uniform plasma distribution in the etching cavity. This local variation in film thickness ensures that the etching rate and depth are uniform across the entire wafer, preventing shrinkage defects at the edges while maintaining the miniaturized capacitor dimensions for high storage density.
2Length of moving object
If the through hole size is reduced to accommodate smaller capacitors, then the capacitance structure size is reduced, but the connection reliability deteriorates due to shrinkage defects
Solution Approach 1:
The patent applies preliminary action by forming the non-uniform first film layer before the etching process. This pre-formed thickness compensation layer ensures that when the etching process occurs, the plasma non-uniformity is already compensated for, resulting in uniform through hole formation from the outset. This prevents shrinkage defects that would otherwise compromise the connection reliability between the capacitance structure and the bit line, allowing for reduced capacitance structure size without sacrificing connection quality.
3Speed
If the plasma distribution in the etching cavity is non-uniform, then the etching speed varies across the wafer, but the etching uniformity deteriorates
Solution Approach 1:
The patent applies parameter changes by modifying the thickness parameter of the first film layer across different regions of the wafer. The first film layer thickness is changed from a uniform value to a gradient distribution, being thinner at the edges and thicker at the center. This parameter variation compensates for the non-uniform plasma distribution, ensuring that the effective etching depth remains uniform across the wafer surface even though the etching speed varies due to plasma non-uniformity. The thickness compensation ensures consistent through hole formation and prevents shrinkage defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces shrinkage defects in semiconductor devices, enhancing the yield by ensuring proper connection of capacitance structures and improving the uniformity of etching processes.
Implementation Method 1
A thickness of the first film layer is reduced so that the thickness of the first film layer at where orthographic projection of the first film layer on the wafer locates at an edge of the wafer is less than a thickness of the first film layer at where orthographic projection of the first film layer on the wafer locates in the middle of the wafer
Data Source
AI summary
A method for preparing method semiconductor device includes: providing a wafer on which a semiconductor structure is formed; forming a stacked film layer structure on a side of the semiconductor structure away from the wafer, a film layer in the stacked film layer structure farthest from the semiconductor structure being a first film layer; reducing a thickness of the first film layer so that the thickness of the first film layer at where orthographic projection of the first film layer on the wafer locates at an edge of the wafer is less than the thickness of the first film layer at where orthographic projection of the first film layer on the wafer locates in middle of the wafer; and patterning the stacked film layer structure to form through holes which communicate to the semiconductor structure.