3D DRAM Trench-TSV Integration Without Wafer Thinning
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Solution Overview
Problem
The complexity and material waste associated with thinning silicon wafers for three-dimensional integrated circuit packaging, which can lead to warpage and deformation, and increases the overall package thickness, hindering high-density and reliable chip stacking.
Innovation Solution
A three-dimensional integrated system for DRAM chips utilizing a top trench, bottom trench, and through silicon via, with specific insulating and copper diffusion barrier layers, and a conductive copper pillar, allowing for efficient electrical connection without the need for silicon wafer thinning, and using a filler to protect the chip from external forces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If silicon wafer is thinned to meet packaging thickness requirements, then package thickness is reduced, but process complexity increases and silicon material is wasted
Solution Approach 1:
Instead of thinning the silicon wafer first and then fabricating TSV structures, the patent inverts the sequence by first forming trenches, then growing silicon dioxide layers, and finally creating TSV structures within the intact silicon substrate. This inversion eliminates the need for wafer thinning while achieving the required package thickness through vertical stacking architecture.
Solution Approach 2:
The patent performs preliminary actions by forming trenches and depositing insulating layers on the silicon substrate before fabricating the TSV structures. This preliminary preparation allows subsequent TSV fabrication to proceed without requiring wafer thinning, thereby simplifying the overall process and preventing material waste.
2Length of stationary object
If silicon wafer is thinned for TSV fabrication, then package thickness is reduced, but silicon material is wasted
Solution Approach 1:
The patent inverts the conventional approach by not thinning the silicon wafer at all. Instead, it forms trenches and TSV structures within the full-thickness silicon substrate, thereby eliminating silicon material waste while still achieving the required package thickness through vertical integration.
Solution Approach 2:
The patent changes the parameter of silicon substrate thickness utilization by maintaining the full substrate thickness and compensating through vertical stacking of functional layers and chips. This parameter change eliminates material waste while achieving the desired compact package dimensions.
3Length of stationary object
If silicon wafer is thinned, then package thickness is reduced, but warpage and deformation occur
Solution Approach 1:
The patent inverts the process sequence to avoid wafer thinning entirely. By forming all structures including TSVs within the intact silicon substrate, the mechanical stability and structural integrity of the silicon wafer are preserved, eliminating warpage and deformation issues.
Solution Approach 2:
The patent provides beforehand cushioning by forming a silicon dioxide insulating layer within trenches before fabricating TSV structures. This layer acts as a buffer that maintains structural integrity and prevents warpage during subsequent processing steps, eliminating the need for wafer thinning.
4Quantity of substance
If conventional TSV interposer technology is used, then stacking density is maximized, but package thickness increases
Solution Approach 1:
The patent merges the TSV interposer structure with the silicon substrate itself by forming trenches and TSVs directly in the substrate. This merging eliminates the need for a separate thinned interposer layer, thereby maintaining high stacking density while reducing overall package thickness.
Solution Approach 2:
The silicon substrate serves multiple functions: it provides mechanical support, hosts the TSV interconnection structures, and contains the insulating layers. This multi-functionality eliminates the need for separate interposer layers, achieving both high stacking density and reduced package thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces process complexity, conserves silicon material, prevents warpage and deformation, maintains high-density packaging, and ensures reliable electrical connections without increasing package thickness, while protecting the chips from external impacts.
Implementation Method 1
a first copper diffusion barrier layer and a copper seed layer, wherein the first insulating medium covers the bottom trench and is discontinuous at the bottom of the through silicon via; the first copper diffusion barrier layer is formed on the first insulating medium; the copper seed layer covers the first copper diffusion barrier layer
Implementation Method 2
the conductive copper pillar covers the second copper diffusion barrier layer on the sidewall of the through silicon via, and completely fills the through silicon via, the top of the conductive copper pillar is in contact with the copper film, and the bottom of the conductive copper pillar is in contact with the copper seed layer
Data Source
AI summary
Disclosed is a three-dimensional integrated system for DRAM chips and a fabrication method thereof. A plurality of trench structures are etched on the front and back of a silicon wafer; then, a TSV structure is etched between the two upper and lower trenches opposite to each other for electrical connection; then, DRAM chips are placed in the trenches, and copper-copper bonding is used to make the chips electrically connected to the TSV structure in a vertical direction; finally, redistribution is done to make the chips in a horizontal direction electrically connected. The invention can make full use of silicon materials, and can avoid problems such as warpage and deformation of an interposer. In addition, placing the chips in the trenches will not increase the overall package thickness, while protecting the chips from external impact.