DRAM Variable Burst Lengths for Data and Metadata Access
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Solution Overview
Problem
Conventional DRAM devices restrict efficient access to data and metadata, limiting the ability to store additional metadata for security and reliability purposes without accessing multiple cache lines.
Innovation Solution
A DRAM device with variable burst lengths and two modes of operation, allowing programmable register settings to adjust burst lengths and column address ranges, supporting simultaneous access of metadata and data, and incorporating on-die error correction code (ECC) for enhanced data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional metadata is stored in separate cache lines, then security and reliability are improved, but access complexity and time increase due to requiring multiple cache line accesses
Solution Approach 1:
The patent combines metadata and data into the same cache line, allowing both to be accessed simultaneously in a single memory operation. This merging eliminates the need for separate cache line accesses that would otherwise be required to retrieve both data and its associated metadata, thereby reducing access time while maintaining security and reliability.
Solution Approach 2:
The cache line is designed to serve multiple functions by simultaneously carrying both data and metadata. This multi-functionality allows the memory system to retrieve authenticated data and its associated metadata (such as access permissions or integrity information) in a single operation, improving efficiency without compromising security requirements.
2Productivity
If burst length is extended to accommodate metadata, then data access efficiency is improved, but device complexity increases due to variable burst length requirements
Solution Approach 1:
The patent implements variable burst lengths by changing the parameter of burst length to accommodate different metadata sizes. The memory device can dynamically adjust the burst length within a cache line based on the amount of metadata that needs to be stored and transmitted, allowing efficient data access while adapting to different security and reliability requirements without requiring a completely complex redesign.
Data Source
AI summary
Technologies for dynamic random access memory (DRAM) devices with variable burst lengths are described. One DRAM device includes a first mode of operation having a first burst length and a first column address range, and a second mode of operation having a second burst length and a second column address range. Only one of the first burst length and the second burst length is a power of two. A first product of the first column address range and the first burst length and a second product of the second column address range and the second burst length are substantially the same. The DRAM device includes an error correction code (ECC) block to generate, receive, and store ECC parity associated with data in the first mode of operation and the second mode of operation.