DRAM Vertical ECC Architecture for Soft-Error Correction
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Solution Overview
Problem
The scaling of silicon transistor and process technology in DRAM devices increases their susceptibility to radiation-induced soft-errors and weak-cells, compromising memory cell reliability, and existing error correction methods like Horizontal ECC require significant infrastructure changes and redundant devices, leading to high overhead.
Innovation Solution
The implementation of Vertical ECC, which integrates error correcting modules within data buffers and DRAM devices to correct single or double bit errors directly, using additional check bits to encode and decode data bursts, reducing the need for redundant devices and minimizing host memory controller changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Horizontal ECC is used to correct errors in DRAM devices, then error correction capability is improved, but infrastructure changes and redundant devices are required leading to high overhead
Solution Approach 1:
The patent divides the error correction function into vertical segments, with each DRAM device having its own independent error correction code (ECC) bits. This segmentation allows error correction to be performed independently for each device without requiring system-wide infrastructure changes or redundant devices, thus maintaining reliability while reducing overhead.
Solution Approach 2:
The patent transitions from horizontal ECC (which operates across multiple devices) to vertical ECC (which operates within each device independently). This dimensional change allows error correction to be performed in a more efficient manner, eliminating the need for redundant devices and infrastructure changes while maintaining error correction capability.
2Productivity
If more DRAM devices are added to increase data bus width, then data throughput is improved, but electrical load on CA bus increases
Solution Approach 1:
The patent introduces an intermediary buffer device that sits between the host controller and multiple DRAM devices. This buffer absorbs and manages the electrical load on the command/address (CA) bus, allowing multiple DRAM devices to be connected without overwhelming the CA bus. The buffer acts as a mediator that enables high data throughput while protecting the CA bus from excessive electrical stress.
3Reliability
If error correction is performed on multiple DRAM devices simultaneously, then overall error correction capability is improved, but latency and bandwidth impact increases
Solution Approach 1:
The patent segments the error correction process into independent vertical units, where each DRAM device is corrected independently using its own ECC bits. This segmentation allows error correction to be performed in parallel for each device without coordinating across multiple devices, significantly reducing latency and bandwidth impact while maintaining overall error correction capability.
Solution Approach 2:
Each DRAM device performs its own error correction independently using vertically organized ECC bits stored within the same device. This self-service approach eliminates the need for cross-device communication and coordination during error correction, reducing both latency and bandwidth consumption while maintaining reliable error correction across the entire memory system.
Data Source
AI summary
Techniques for operating a DIMM apparatus. The apparatus comprises a plurality of DRAM devices numbered from 0 through N−1, where N is an integer greater than seven (7), each of the DRAM devices is configured in a substrate module; a buffer integrated circuit device comprising a plurality of data buffers (DB) numbered from 0 through N−1, where N is an integer greater than seven (7), each of the data buffers corresponds to one of the DRAM devices; and a plurality of error correcting modules (“ECMs”) associated with the plurality of DRAM devices.