Differential Voltage Coding in DRAM for Longer Refresh Cycles
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) faces challenges in storage density and energy consumption due to the need for frequent refresh operations to maintain data integrity, as capacitors used in DRAM cells lose charge over time, requiring short refresh intervals and high energy expenditure.
Innovation Solution
The implementation of a voltage code storage system that encodes n bits of data into k bits, allowing for storage of codewords with k > n, where each memory cell can store charge at three or more levels, enabling longer refresh intervals without data loss, and relaxes the constraints on charge retention characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional DRAM with binary charge levels is used, then storage density is limited, but refresh operations must be performed frequently to maintain data integrity
Solution Approach 1:
The patent changes the fundamental parameter of charge levels from binary (2 levels) to multi-level (3 or more levels). Each memory cell stores a voltage representing a codeword entry from a voltage code, where voltages are drawn from a set of possible values including at least three distinct levels. This parameter change enables higher storage density while reducing refresh frequency requirements.
Solution Approach 2:
The patent segments the storage system into groups of memory cells where each group stores a codeword of multiple entries. Instead of storing individual bits in isolation, the system organizes storage into structured codewords with specific voltage relationships, enabling error detection and correction capabilities that reduce refresh operations.
2Reliability
If short refresh intervals are used to maintain data integrity, then data loss is prevented, but energy consumption increases
Solution Approach 1:
The patent implements feedback through voltage codes with constant sum properties. The encoded voltage patterns provide inherent error detection and correction capabilities, allowing the system to detect and correct leakage-induced errors without requiring frequent refresh operations. This feedback mechanism maintains data integrity while reducing refresh frequency.
Solution Approach 2:
The patent applies beforehand cushioning by using redundant voltage levels and codeword structures that can tolerate charge leakage. The multi-level voltage system and code design provide a buffer against data loss, allowing longer intervals between refresh operations while maintaining reliability.
3Quantity of substance
If more memory cells are used to store data, then storage capacity increases, but device complexity increases
Solution Approach 1:
The patent applies universality by using the same memory cell structure for both high-density storage and error correction functions. The voltage code encoding and decoding logic provides multiple functions including data storage, error detection, and error correction, reducing the need for separate dedicated circuits and minimizing overall device complexity.
4Device complexity
If conventional binary storage is used, then device simplicity is maintained, but storage density is limited
Solution Approach 1:
The patent changes the voltage parameter from binary to multi-level, allowing each memory cell to represent multiple states. This parameter change increases storage density while maintaining relatively simple memory cell structures, as the fundamental cell architecture remains similar to conventional DRAM.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory density and reduces energy consumption by allowing longer refresh cycles and more efficient data storage, as the voltage code is invariant to common leakage, enabling reliable data retrieval without the need for external references.
Implementation Method 1
each memory cell of a group is capable of storing charge at three or more specified levels
Implementation Method 2
capacitors used to store information exhibit leakage and therefore need to be refreshed to guarantee the integrity of the data stored
Data Source
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AI summary
A storage device stores data in groups of memory cells using vectors corresponding to voltage code codewords, each codeword having k entries. Entries have values selected from a set of at least three entry values and 2n distinct inputs can be encoded into k-entry codewords for some n > k. A vector storage element comprising k cells can store an k electrical quantities (voltage, current, etc.) corresponding to a codeword. The voltage code is such that, for at least one position of a vector, there are at least three vectors having distinct entry values at that position and, for at least a subset of the possible codewords, the sum of the entry values over the positions of the each vector is constant from vector to vector in that subset. The storage device might be an integrated circuit device, a discrete memory device, or a device having embedded memory.