DRAM VRT Detection via Multi-Stage Retention Testing
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Solution Overview
Problem
Current methods for detecting Dynamic Random Access Memory (DRAM) chips with Variable Retention Time (VRT) issues are inefficient, as a chip may be incorrectly classified as normal in initial tests but later show data loss, making it difficult to accurately identify affected chips.
Innovation Solution
A multi-stage memory inspecting method involving first, second, and third data retention time tests, followed by statistical analysis of the results to identify final qualified memory chips, using a testing machine and computer system to assess DRAM chips and determine their retention times and perform statistical analysis to identify chips with VRT issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple data retention time tests are performed on memory chips, then the accuracy of detecting VRT issues is improved, but the testing time and complexity increase
Solution Approach 1:
The testing process is divided into three distinct stages: first data retention time test, second data retention time test, and third data retention time test. Each stage targets specific retention time characteristics, allowing systematic detection of VRT issues while managing testing time through structured segmentation rather than exhaustive testing.
Solution Approach 2:
The first data retention time test serves as a preliminary screening to identify chips with potential VRT issues before proceeding to more comprehensive second and third tests. This preliminary action filters out obviously defective chips, reducing the overall testing burden while maintaining detection accuracy.
2Reliability
If multiple data retention time tests are performed on memory chips, then the reliability of VRT detection is improved, but the device complexity increases
Solution Approach 1:
The testing process is divided into three distinct stages: first data retention time test, second data retention time test, and third data retention time test. Each stage targets specific retention time characteristics, allowing systematic detection of VRT issues while managing testing time through structured segmentation rather than exhaustive testing.
Solution Approach 2:
The testing methodology incorporates feedback mechanisms where results from the first test influence the second test, and results from the second test influence the third test. This feedback loop allows dynamic adjustment of testing depth based on initial findings, improving reliability while preventing unnecessary complexity through conditional testing paths.
Data Source
AI summary
A memory inspecting method and a memory inspecting system are proposed. The memory inspecting system includes a testing machine and a computer system. The memory inspecting method includes: performing a first data retention time test on a plurality of memory chips to obtain a plurality of first qualified memory chips; performing a second data retention time test on the first qualified memory chips to obtain a plurality of second qualified memory chips; performing a third data retention time test on the second qualified memory chips to obtain a plurality of third qualified memory chips. Performing a statistical analysis step on the third qualified memory chips according to a first data retention time, a second data retention time and a third data retention time of each of the third qualified memory chips is for obtaining at least one final qualified memory chip.