DRAM Memory and Wire Patterning for Boundary Yield Stability
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Solution Overview
Problem
Existing methods for fabricating DRAM devices face challenges in scaling down size while maintaining high manufacturing yield and preventing pattern failures at the boundary between memory cell and peripheral circuitry regions.
Innovation Solution
A method involving multiple photolithography processes and the use of patterned hard mask layers to form conductive pads and wires simultaneously, with enhanced etching parameters to prevent pattern transfer and failure, reducing the risk of array punch-through and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scaling down DRAM size is pursued to increase density and improve performance, then device density and performance are improved, but manufacturing yield deteriorates due to pattern failures at boundary regions
Solution Approach 1:
The patent divides the substrate into distinct memory cell array region and periphery circuitry region, and applies different patterning strategies to each region. The first photolithography process forms patterns in the memory cell array region while the second process forms patterns in the periphery circuitry region, preventing pattern failures at boundaries and maintaining high manufacturing yield while enabling continued scaling for increased DRAM density.
2Ease of manufacture
If conventional single photolithography process is used to form conductive patterns, then process complexity is low, but pattern failures occur at boundary between memory cell and periphery circuitry regions
Solution Approach 1:
The patent employs two separate photolithography processes: a first process for forming conductive material patterns in the memory cell array region, and a second process for forming conductive material patterns in the periphery circuitry region. This segmentation prevents pattern failures at region boundaries while maintaining overall process feasibility through systematic organization of the multi-step approach.
3Device complexity
If etching parameters are not optimized, then etching process is simple, but array punch-through occurs and pattern transfer fails
Solution Approach 1:
The patent implements optimized etching parameters including controlled etching depth, etching rate, and selective etching conditions to prevent array punch-through and ensure precise pattern transfer. The etching process is carefully tuned to remove only the intended hard mask patterns while preserving underlying structures, achieving high manufacturing precision without excessive process complexity.
Data Source
AI summary
A method for forming a semiconductor memory structure includes the following steps. A first patterned hard mask layer is formed over a conductive material. The first patterned hard mask layer includes first strip patterns and a mesa pattern. The mesa pattern is connected with the first strip patterns. A second patterned hard mask layer is formed over the first patterned hard mask layer. The second patterned hard mask layer includes second strip patterns overlapping the first strip patterns and first wire patterns overlapping the mesa pattern. The first patterned hard mask layer is etched using the second patterned hard mask layer. The remaining portions of the first strip patterns form pad patterns. The remaining portions of the mesa pattern form second wire patterns. The pad patterns and the second wire patterns are transferred into the conductive material.