DRAM Word Line Layout With Larger Contact Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As feature sizes in DRAM devices decrease, the spacing between adjacent word lines (WLs) decreases, making it difficult to set contact structures, increasing contact resistance, and leading to issues like circuit break and short circuits, which affect storage performance.
Innovation Solution
The semiconductor structure manufacturing method involves forming multiple independent trenches in the substrate with different feature sizes in different areas, allowing for varying word line feature sizes. This method reduces the difficulty of setting contact structures, increases the contact area, and stabilizes connections between word lines and contact structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the spacing between adjacent word lines is decreased to increase memory density, then the storage capacity is improved, but the contact resistance increases and the difficulty of setting contact structures increases
Solution Approach 1:
The patent divides the contact structure into multiple segments: a first contact structure and a second contact structure. The first contact structure is formed in the first trench and connects to the first word line, while the second contact structure is formed in the second trench and connects to the second word line. This segmentation allows each contact structure to be independently optimized and formed, reducing the overall difficulty of contact structure setting while maintaining high memory density.
Solution Approach 2:
The patent introduces an intermediary approach by using separate trenches and contact structures for adjacent word lines. Instead of forming a single contact structure that would be difficult to position precisely, the method uses multiple independent contact structures that can be formed with relaxed alignment requirements, thereby reducing contact resistance and setting difficulty.
2Quantity of substance
If the contact structure is formed in narrow spacing between word lines, then the memory density is improved, but the contact resistance increases
Solution Approach 1:
The contact path is segmented into multiple sections with separate contact structures. Each contact structure connects to its respective word line through an independent trench, allowing the current to flow through multiple parallel paths rather than a single narrow contact point. This segmentation reduces the effective contact resistance while maintaining high memory density.
Solution Approach 2:
The patent combines multiple contact structures (first contact structure and second contact structure) to form a comprehensive contact network. By merging these separate contact structures into the overall word line connection system, the total contact area is increased, which reduces the overall contact resistance while maintaining the narrow spacing between word lines for high memory density.
3Quantity of substance
If the contact structure is formed with smaller features to match reduced word line spacing, then the memory density is improved, but the likelihood of circuit break and short circuit increases
Solution Approach 1:
The patent segments the contact formation process into multiple independent steps, forming the first contact structure and second contact structure separately in their respective trenches. This segmentation allows each contact structure to be formed with adequate dimensions and spacing, reducing the likelihood of circuit breaks and shorts while still achieving high memory density through the overall compact layout.
Solution Approach 2:
The patent employs beforehand cushioning by forming separate trenches and contact structures for adjacent word lines. This design creates inherent spacing and isolation between contact structures, providing a buffer that prevents circuit breaks and short circuits from occurring, even as feature sizes are reduced to increase memory density.
Data Source
Figure 1~2
Figure 3~5
Figure 6~8
AI summary
Provided are a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method includes: a substrate is provided, which includes a first area and a second area set adjacent to each other; multiple trenches, which are arranged at intervals along a first direction, are formed in both the first area and the second area of the substrate; a word line (WL) is formed in each of the multiple trenches, a feature size of the WL in the first area is different from that of the WL in the second area; and a contact structure is formed on the WL with the greater feature size. The disclosure may reduce the difficulty of setting a contact structure, reduce contact resistance at the joint of the contact structure and the WL, ensure the stability of connection between them, and improve the performance of the semiconductor structure.