3D Stacked DRAM Word Line Isolation Using Segmented Active Layers
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Solution Overview
Problem
The performance of 3D stacked DRAM is limited due to interconnection between word lines, which is caused by the small distance between adjacent layers of word lines during the manufacturing process.
Innovation Solution
A semiconductor structure manufacturing method that involves forming active layers and sacrificial layers alternately, with specific distances between them, and using isolation layers to divide the active layers into active structures. This method ensures that the first dielectric layer can fill the spaces between active groups, isolating the word lines and preventing interconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between adjacent layers of word lines is reduced to increase integration, then the integration level is improved, but interconnection between word lines occurs causing performance degradation
Solution Approach 1:
The patent applies segmentation by dividing the continuous active layer into multiple discrete active structures using isolation layers. This segmentation creates physical separation between adjacent word lines, preventing interconnection while maintaining high integration. The isolation layers act as barriers that segment the structure vertically, allowing word lines to be closely spaced without direct contact.
Solution Approach 2:
The patent introduces isolation layers as intermediary elements between adjacent active layers. These isolation layers serve as mediators that prevent direct contact between word lines from different layers, eliminating the interconnection problem while allowing the word lines to remain in close proximity for high integration.
2Reliability
If isolation layers are used to divide active layers into active structures, then interconnection between word lines is prevented, but the manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming isolation layers between active layers during the manufacturing process before the word lines are fully operational. This preliminary placement of isolation layers prevents interconnection issues from arising in the first place, rather than requiring complex corrective measures later in the manufacturing process or operation.
Data Source
AI summary
Embodiments of the present disclosure relate to the field of semiconductors, and provide a method of manufacturing a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a base, and forming active layers and sacrificial layers on the base, wherein two adjacent ones of the active layers constitute an active group, there is a first distance between the active layers in the active group, there is a second distance between adjacent ones of active groups, and the first distance is greater than the second distance; forming isolation layers, wherein each isolation layer penetrates through all the active layers and all the sacrificial layers, and the isolation layers divide each of the active layers into a plurality of active structures; removing a part of the isolation layers in the word line region and a part of the sacrificial layers located in the word line region.