DRAM Word Line Driver Layout for Higher Density and Speed
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing Dynamic Random Access Memory (DRAM) devices face challenges in achieving high integration and efficiency due to limitations in the design of word line drivers and peripheral circuits, which affect the overall performance and density of the memory devices.
Innovation Solution
The implementation of a memory device with a drive circuit comprising a main driver connected to more than 8 word line drivers, including a pre-charge circuit and an output circuit with transistor size ratios optimized for enhanced driving capability, and a stacked layout of memory cell arrays and peripheral circuits on different substrates to improve integration and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the number of word line drivers connected to a main driver is increased beyond 8, then the integration level and driving speed are enhanced, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The drive circuit is segmented into a main driver and multiple word line drivers (more than 8), where each word line driver independently controls a specific word line. This segmentation allows the system to achieve high driving speed for multiple word lines while maintaining manageable complexity through modular design, resolving the contradiction between speed enhancement and circuit complexity.
2Power
If transistor size in the output circuit is increased relative to the pre-charge circuit, then the driving capability is enhanced, but the area occupied by the drive circuit increases
Solution Approach 1:
The patent applies different transistor sizes to different functional blocks within the drive circuit. Specifically, transistors in the output circuit are made larger than those in the pre-charge circuit, creating local quality differences that optimize driving capability where needed while minimizing area consumption in other regions, thus resolving the contradiction between power and area.
3Productivity
If memory cell arrays and peripheral circuits are stacked on different substrates, then the integration level is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking by placing memory cell arrays and peripheral circuits on different substrates in the vertical dimension. This dimensional change enables higher integration levels by utilizing space more efficiently, while the modular substrate approach actually simplifies manufacturing compared to attempting to integrate everything on a single plane.
Data Source
AI summary
According to one aspect of the present disclosure, a memory device is provided. The memory device may include a memory cell array. The memory device may include a plurality of word lines coupled with the memory cell array. The memory device may include a peripheral circuit coupled with the memory cell array through the plurality of word lines and comprising a drive circuit. The drive circuit may include a main driver and a plurality of word line drivers. Each of the word line drivers may be correspondingly coupled with each of the word lines. The main driver may be connected to n word line drivers, wherein n is an integer greater than 8.