3D DRAM Word Line Fabrication Using Dummy Line Templates
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Solution Overview
Problem
The performance of 3D stacked DRAM needs improvement due to issues of false interconnections or disconnections in word lines caused by varying thicknesses of conductive material deposition, leading to potential disconnections or interconnections at different locations.
Innovation Solution
A method involving the formation of dummy word line structures and isolation layers to standardize the shape of word lines, using isolation layers to regulate the shape and position of initial word lines, and increasing the process window for manufacturing, thereby avoiding disconnections and interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conductive material is deposited to form word lines, then the word lines are formed to cover active structures, but the thickness varies at different locations causing false interconnections or disconnections
Solution Approach 1:
The patent applies preliminary action by forming dummy word line structures before the actual word lines. These dummy structures serve as templates that define the precise location and thickness of subsequent word lines through conformal deposition, ensuring uniform thickness and preventing connection defects.
Solution Approach 2:
The dummy word line structures act as intermediary elements that mediate between the deposition process and the final word line formation. They provide a physical template that ensures consistent material deposition thickness, thereby guaranteeing reliable electrical connections.
2Productivity
If multiple layers of transistors are stacked to form 3D stacked DRAM, then the integration level increases and cost per unit area decreases, but the performance needs improvement
Solution Approach 1:
The patent segments the word line formation process into distinct stages: forming dummy word line structures, depositing isolation layers, and then forming actual word lines. This segmentation allows precise control over each layer's properties, improving overall device performance while maintaining high integration.
Solution Approach 2:
The patent changes physical parameters by using conformal deposition techniques that control film thickness based on the underlying dummy structure geometry. This parameter control ensures uniform word line thickness across the 3D stacked structure, improving performance reliability.
3Manufacturing precision
If dummy word line structures are formed and then removed, then the space is prepared for initial word lines, but additional process steps are required
Solution Approach 1:
The patent uses copying by creating dummy word line structures that replicate the desired final word line geometry. These copies serve as templates for subsequent conformal deposition, ensuring accurate positioning and consistent dimensions without requiring complex direct patterning.
Data Source
AI summary
A method of manufacturing a semiconductor structure is disclosed. The semiconductor structure includes a transistor area, which includes a first source-drain area and a word line region. The method includes forming an active layer on a substrate, and the active layer of the transistor region includes a plurality of active structures. A dummy word line structure covering the active structure of the same layer is formed in the first source drain region and the word line region. The first isolation layers arranged alternately with the dummy word line structures in the third direction are formed. Then the dummy word line structure is removed. An initial dielectric layer is formed on the surface of the active structure of the first source-drain region and the word line region. An initial word line is formed on the surface of the initial dielectric layer. The initial word line and the initial dielectric layer located in the first source and drain region are removed.