DRAM Word Line Air-Gap Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices shrink, the increased parasitic capacitance between word line structures in DRAMs leads to higher power consumption, which is a challenge in the development of compact and efficient memory for mobile devices.
Innovation Solution
A semiconductor structure is formed with air gaps between word line structures, reducing parasitic capacitance and power consumption, and a sealing layer is used to prevent structural breakdown at the air gap openings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the volume of semiconductor device is reduced to increase integration, then the number of word line structures per unit area increases, but the spacing between word line structures becomes smaller and parasitic capacitance increases
Solution Approach 1:
The patent introduces air gaps (porous structure) between adjacent word line structures. These air gaps reduce the parasitic capacitance between neighboring conductive lines by replacing the traditional dielectric material with air, which has a lower dielectric constant. This allows for higher integration density while maintaining lower power consumption by reducing the capacitive coupling between closely spaced word lines.
2Use of energy by moving object
If air gaps are formed between word line structures to reduce parasitic capacitance, then power consumption decreases, but the air gap openings may cause structural breakdown
Solution Approach 1:
The patent applies a sealing layer over the air gap openings before subsequent processing steps. This sealing layer prevents structural breakdown by protecting the air gap region from mechanical stress, chemical etchants, and other processing conditions that could cause collapse or damage to the air gap structure. The sealing is performed in advance to ensure structural integrity throughout the manufacturing process.
3Area of stationary object
If the spacing between word line structures is reduced to increase integration, then device area decreases, but parasitic capacitance between word line structures increases
Solution Approach 1:
The patent utilizes air gaps (porous structure) between word line structures to reduce parasitic capacitance. By introducing these air-filled spaces, the dielectric constant between adjacent conductors is reduced from that of solid dielectric materials to approximately 1 (air), thereby minimizing capacitive coupling. This enables closer spacing of word lines and reduces overall device area while maintaining low parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces parasitic capacitance and power consumption while enhancing product stability and integration, addressing the limitations of current DRAM technology.
Implementation Method 1
the parasitic capacitance between the word line structures is increased
Data Source
AI summary
A semiconductor structure, a method for forming a semiconductor structure, and a memory are provided. The method for forming the semiconductor structure in the disclosure includes: providing a base, the base including a substrate and an insulating dielectric layer, the substrate including a plurality of first trenches spaced apart from each other in a first direction, and the insulating dielectric layer being filled in each of the plurality of first trenches; patterning and etching the base to form a plurality of second trenches spaced apart from each other in a second direction, the second direction intersecting with the first direction; forming a word line structure in each of the plurality of second trenches; forming an air gap between each two adjacent word line structures of a plurality of word line structures; and sealing the air gap.