DRAM Word Line Layout With Larger Peripheral Contacts
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Solution Overview
Problem
As feature sizes of DRAM devices decrease, the spacing between adjacent word lines (WLs) decreases, making it difficult to set contact structures and increasing contact resistance, leading to circuit breaks and short circuits, which affects storage performance.
Innovation Solution
The method involves forming multiple trenches in a substrate with different structure densities in adjacent areas, resulting in varying feature sizes of WLs, with a larger feature size in the peripheral area to facilitate easier contact structure formation and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the feature size of DRAM device is decreased, then the integration density is improved, but the spacing between adjacent WLs decreases making contact structure formation difficult and contact resistance increases
Solution Approach 1:
The patent applies local quality by creating different trench depths in different regions of the substrate. The peripheral area has deeper trenches than the array area, allowing the WL in the peripheral area to have a larger cross-sectional area where contact structures are formed, while maintaining smaller feature sizes in the array area for high integration density.
Solution Approach 2:
The patent introduces depth as an additional dimension to solve the contact resistance problem. By varying the trench depth in the vertical dimension across different regions, the WL can have different cross-sectional areas without changing the planar feature size, thus reducing contact resistance while maintaining integration density.
2Quantity of substance
If the feature size of DRAM device is decreased, then the integration density is improved, but the contact resistance increases leading to circuit breaks and short circuits
Solution Approach 1:
The patent creates locally optimized structures by making trenches in the peripheral area deeper than those in the array area. This allows the WL to have a larger cross-sectional area specifically at contact points, reducing contact resistance and improving reliability, while maintaining small feature sizes elsewhere for high integration density.
Solution Approach 2:
By utilizing the vertical dimension through varying trench depths, the patent increases the WL cross-sectional area at contact regions without increasing the planar footprint. This dimensional approach effectively reduces contact resistance and prevents circuit failures while preserving integration density.
3Quantity of substance
If the spacing between adjacent WLs is decreased, then the integration density is improved, but the difficulty of setting contact structure increases
Solution Approach 1:
The patent simplifies contact structure setting by creating deeper trenches locally in the peripheral area where contact structures are formed. This local structural differentiation provides larger contact areas and easier alignment, reducing the complexity of contact structure formation despite tight spacing between WLs in the array area.
Data Source
AI summary
Provided are a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method includes: a substrate is provided, which includes a first area and a second area set adjacent to each other; multiple trenches, which are arranged at intervals along a first direction, are formed in both the first area and the second area of the substrate; a word line (WL) is formed in each of the multiple trenches, a feature size of the WL in the first area is different from that of the WL in the second area; and a contact structure is formed on the WL with the greater feature size.