DRAM Write Arbitration Using Bank Group Masking
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Solution Overview
Problem
JEDEC specifications for DDR DRAMs with additional features and complexity pose challenges for DRAM memory controllers, making it difficult to optimize memory access efficiency without causing excessive size and cost, and requiring complete re-designs.
Innovation Solution
A memory controller with a bank group tracking circuit that tracks bank group numbers of prior write requests and prevents selection of write requests and associated activate commands to these groups for a designated period, allowing efficient scheduling and reducing the need for re-designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DRAM memory controllers are designed to optimize memory access efficiency for DDR DRAMs with additional features and complexity, then memory access efficiency is improved, but device size and cost increase excessively
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing optimal memory access schedules in lookup tables before runtime. The controller pre-determines command sequences for different access patterns, allowing efficient memory access without complex real-time arbitration logic, thus improving productivity while controlling device complexity
Solution Approach 2:
The patent uses copying by implementing simplified model controllers that replicate essential arbitration functionality. These model controllers generate reference schedules that are stored and reused, avoiding the need for full-scale complex arbitration logic in the actual controller, thereby reducing device size and cost while maintaining memory access efficiency
2Productivity
If traditional arbitration methods are used for DDR DRAMs with additional features, then implementation is simpler, but memory access efficiency deteriorates
Solution Approach 1:
The patent pre-calculates optimal command schedules and stores them in lookup tables based on different memory access patterns. During operation, the controller simply retrieves pre-computed schedules rather than performing complex real-time arbitration, thereby achieving high memory access efficiency without requiring complex arbitration mechanisms
Solution Approach 2:
The patent changes the operational parameters of the arbitration system by switching from dynamic real-time arbitration to static pre-computed scheduling. This parameter change allows the system to achieve high memory access efficiency using simple lookup table operations instead of complex arbitration logic
Data Source
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AI summary
A memory controller includes an arbiter for selecting memory requests from a command queue for transmission to a DRAM memory. The arbiter includes a bank group tracking circuit that tracks bank group numbers of three or more prior write requests selected by the arbiter. The arbiter also includes a selection circuit that selects requests to be issued from the command queue, and prevents selection of write requests and associated activate commands to the tracked bank group numbers unless no other write request is eligible in the command queue. The bank group tracking circuit indicates that a prior write request and associated activate commands are eligible to be issued after a number of clock cycles has passed corresponding to a minimum write-to-write timing period for the bank group of the prior write request.