DRAM Write Training Using PRBS Checking Without Data Storage
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Solution Overview
Problem
As DRAM memory devices increase in speed, the length of data patterns required for write training operations becomes longer, increasing the time and storage requirements, which reduces available memory space and bandwidth for other operations.
Innovation Solution
The proposed method involves using a pseudo-random bit sequence (PRBS) generated by linear feedback shift registers (LFSRs) to check the incoming write training pattern against the output of the LFSR, allowing all pins of the data interface to be trained concurrently, eliminating the need to store and read lengthy data patterns from the memory device, and using a PRBS checker implemented with XOR logic to determine the success of the write training operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the length of data patterns for write training operations is increased to improve training accuracy, then the reliability of write training is improved, but the time required for write training operations and the storage requirements increase
Solution Approach 1:
The patent extracts only the essential information needed for write training verification (pass/fail result) while discarding the lengthy data patterns. Instead of storing and reading back complete data patterns, the system uses a PRBS checker to generate and compare pseudo-random bit sequences, extracting only the verification result which indicates whether write training succeeded.
Solution Approach 2:
The patent uses a PRBS (pseudo-random bit sequence) generator to create a copy of the training pattern locally on the memory device side. This copied pattern is then compared with the received pattern using XOR logic, eliminating the need to transfer the actual lengthy training data back to the controller for verification.
2Reliability
If the length of data patterns for write training operations is increased to improve training accuracy, then the reliability of write training is improved, but the storage requirements and reduction of available memory space increase
Solution Approach 1:
The patent extracts only the essential information needed for write training verification (pass/fail result) while discarding the lengthy data patterns. Instead of storing and reading back complete data patterns, the system uses a PRBS checker to generate and compare pseudo-random bit sequences, extracting only the verification result which indicates whether write training succeeded.
3Reliability
If the length of data patterns for write training operations is increased to improve training accuracy, then the reliability of write training is improved, but the bandwidth available for other operations decreases
Solution Approach 1:
The patent extracts only the essential information needed for write training verification (pass/fail result) while discarding the lengthy data patterns. Instead of storing and reading back complete data patterns, the system uses a PRBS checker to generate and compare pseudo-random bit sequences, extracting only the verification result which indicates whether write training succeeded.
Solution Approach 2:
The patent enables continuous memory operations during write training by eliminating the need to pause bandwidth for reading back lengthy training patterns. The PRBS-based verification method allows the memory system to maintain continuous useful action since only minimal verification data needs to be processed, keeping the data interface available for other productive operations.
4Productivity
If all pins of the data interface are trained concurrently to reduce training time, then the productivity of write training is improved, but the complexity of the training system increases
Solution Approach 1:
The patent merges the training verification function into the existing data interface by utilizing the same pins and signal paths for both normal data operations and write training verification. The PRBS checker is integrated into the data interface logic, allowing concurrent training of all pins without requiring separate verification infrastructure, thus reducing overall system complexity despite the parallel training capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the time required for write training operations by half, as only a pass/fail result is needed, and trains all data interface pins in parallel, significantly shortening the training time compared to traditional methods.
Implementation Method 1
a pseudo-random bit sequence (PRBS) generated by linear feedback shift registers (LFSRs) to check the incoming write training pattern against the output of the LFSR
Implementation Method 2
using a PRBS checker implemented with XOR logic to determine the success of the write training operation
Data Source
AI summary
Various embodiments include a memory device that is capable of performing write training operations, to determine that certain timing conditions are met, without storing data patterns in memory. Prior approaches for write training involve storing a long data pattern into the memory followed by reading the long data pattern to determine whether the data was written to memory correctly. Instead, the disclosed memory device generates a data pattern within the memory device that matches the data pattern being transmitted to the memory device by an external memory controller. If the data pattern generated by the memory device matches the data pattern received from the memory controller, then the memory device stores a pass status in a register. If the data patterns do not match, then the memory device stores a pass status in a register. The memory controller reads the register to determine whether the write training passed or failed.