DRAM Write Training Using PRBS Checks Without Pattern Storage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing DRAM write training techniques require lengthy data patterns to be stored and read multiple times, consuming significant memory space and reducing bandwidth, and as DRAM speeds increase, meeting setup and hold time becomes increasingly difficult.
Innovation Solution
Implementing a pseudorandom bit sequence (PRBS) checker that generates and compares data patterns on input/output pins using linear feedback shift registers (LFSRs) to determine write training success without storing the patterns in the DRAM, allowing concurrent training of all pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lengthy data patterns are stored and read multiple times in DRAM for write training, then training reliability is improved, but memory space consumption increases and bandwidth is reduced
Solution Approach 1:
The patent extracts the data pattern storage function from the DRAM memory device and relocates it to the memory controller. The memory controller generates and stores the lengthy data patterns locally, while the DRAM only needs to read and write the patterns during training operations. This separation eliminates the need for DRAM to store training patterns, resolving the contradiction between training reliability and memory space consumption.
Solution Approach 2:
The memory controller acts as an intermediary between the training system and DRAM. It generates the data patterns using a pseudorandom bit sequence generator, buffers them in its own memory, and then transfers them to DRAM for training operations. This intermediary approach allows the DRAM to focus solely on executing training commands without bearing the burden of storing lengthy patterns.
2Reliability
If lengthy data patterns are stored and read multiple times in DRAM for write training, then training reliability is improved, but training time increases and bandwidth is reduced
Solution Approach 1:
The memory controller performs preliminary action by generating and buffering the lengthy data patterns before they are needed for DRAM training. The pseudorandom bit sequence generator creates the patterns in advance, and the memory controller stores them in its internal memory buffer. This allows the DRAM training operations to proceed more efficiently without repeatedly reading from external sources, thereby reducing training time while maintaining reliability.
3Speed
If DRAM speed increases, then data transfer rate is improved, but meeting setup and hold time becomes more difficult
Solution Approach 1:
The patent implements feedback mechanisms during write training operations where the memory controller monitors the training results and adjusts timing parameters accordingly. The training process includes reading back data from DRAM and comparing it with expected values, allowing the system to detect timing violations and automatically adjust setup and hold times. This feedback loop enables the system to maintain reliability even as DRAM operating speed increases.
Data Source
AI summary
Various embodiments include a memory device that is capable of performing write training operations. Prior approaches for write training involve storing a long data pattern into the memory followed by reading the long data pattern to determine whether the data was written to memory correctly. Instead, the disclosed memory device stores a first data pattern (e.g., in a FIFO memory within the memory device) or generates the first data pattern (e.g., using PRBS) that is compared with a second data pattern being transmitted to the memory device by an external memory controller. If data patterns match, then the memory device stores a pass status in a register, otherwise a fail status is stored in the register. The memory controller reads the register to determine whether the write training passed or failed.