DRAM Bank Back-to-Back Write Buffering
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern Dynamic Random Access Memory (DRAM) designs face performance degradation due to the mismatch between internal prefetch size and external data transfer size during back-to-back write operations, leading to inefficiencies in error correction and increased latency.
Innovation Solution
Implementing buffering mechanisms at the memory device to store data until subsequent writes are received, allowing for efficient error correction and reducing the need for internal read-modify-write operations by calculating error correction values based on combined data chunks, and selectively performing ECC calculations for single or multiple chunks of data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If internal prefetch size is increased to improve data transfer efficiency, then bandwidth utilization is improved, but latency increases during back-to-back write operations
Solution Approach 1:
The patent applies preliminary action by pre-fetching data into an internal buffer before write operations are completed. The buffer holds pre-fetched data chunks that can be immediately used for subsequent writes, eliminating the need to wait for external data transfers and reducing command-to-command latency while maintaining high bandwidth utilization.
2Reliability
If error correction is performed on each data chunk individually, then error detection reliability is improved, but operational overhead increases
Solution Approach 1:
The patent merges multiple small data chunks into a larger combined data structure before performing error correction. Instead of calculating ECC for each small chunk separately, the system combines chunks in the buffer and performs a single ECC calculation on the merged data, reducing the number of operations and overhead while maintaining error detection reliability through the use of SECDED codes on the combined data.
3Manufacturing precision
If internal read-modify-write operations are performed to maintain data integrity, then data accuracy is improved, but write performance deteriorates
Solution Approach 1:
The patent introduces an internal buffer as an intermediary between external data transfers and the memory array. The buffer accumulates pre-fetched data and allows write operations to proceed against buffered data without requiring immediate read-modify-write cycles on the memory array itself, thereby maintaining data accuracy while improving write performance by decoupling the write operation from array access.
Data Source
AI summary
Techniques and mechanisms to provide write access to a memory device. In an embodiment, a memory controller sends commands to a memory device which comprises multiple memory banks. The memory controller further sends a signal specifying that the commands include back-to-back write commands each to access the same memory bank. In response to the signal, the memory device buffers first data of a first write command, wherein the first data is buffered at least until the memory device receives second data of a second write command. Error correction information is calculated for a combination of the first data and second data, and the combination is written to the memory bank. In another embodiment, buffering of the first data and combining of the first data with the second data is performed, based on the signal from the memory controller, in lieu of read-modify-write processing of the first data.