DRAM Bank Assignment via Packet Segmentation

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Solution Overview

Problem

Network devices face challenges in optimizing memory utilization and reducing latency when handling variable-length packets, as existing DRAM technologies are limited by row cycle time and inefficient bank utilization.

Innovation Solution

A network storage system with an address adjusting module that segments packets into sections, overwrites bank IDs to distribute data across multiple banks in a cyclic and random or smart bank mode, optimizing interleaving and reducing latency by writing to adjacent banks, thereby improving memory utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is written to multiple banks in round-robin fashion, then memory utilization is optimized, but latency increases due to row cycle time limitations

Engineering Contradiction:
Improvememory utilizationVSAvoidlatency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments packets into multiple sections and distributes them across different memory banks using bank ID overwriting. This segmentation allows parallel access to multiple banks, optimizing memory utilization while managing latency through intelligent bank selection and cyclic writing patterns.

Inventive Principle:
Principle #1Segmentation

2Productivity

If packets are segmented and distributed across multiple banks, then memory utilization improves, but system complexity increases

Engineering Contradiction:
Improvememory utilizationVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The address adjusting module automatically performs bank ID overwriting and cyclic bank selection without requiring complex external control logic. The system self-manages the distribution of packet sections across banks, reducing overall system complexity while maintaining high memory utilization.

Inventive Principle:
Principle #25Self-service

3Speed

If round-robin bank allocation is used, then parallel access is optimized, but performance degrades when handling variable-length packets

Engineering Contradiction:
Improveparallel access speedVSAvoidpacket handling adaptability
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic bank selection through the address adjusting module, which adaptively determines the starting bank ID and manages cyclic writing patterns. This dynamic approach allows the system to maintain optimized parallel access while flexibly adapting to variable-length packets and different traffic patterns.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8209458B1System and method for DRAM bank assignment
Publication Date: 2012.06.26 MARVELL ISRAEL (M L S L) LTD
  • US8209458B1 patent drawing
  • US8209458B1 patent drawing
  • US8209458B1 patent drawing

AI summary

A network storage system includes an address adjusting module that includes a segmented packet receiver module that receives M sections of a segmented packet, where M is an integer greater than one. A bank identification (ID) overwriter module overwrites a bank ID of at least one of the M sections of the packet with a control bank ID that is different than the bank ID.