DRAM-Less Garbage Collection Using Split Volatile Memory Buffers

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Solution Overview

Problem

Existing storage systems face challenges in efficiently performing garbage collection without Dynamic Random Access Memory (DRAM), which can lead to unexpected data modifications during the process, affecting overall performance.

Innovation Solution

A DRAM-less storage system that partitions source data into multiple portions and temporarily stores them in volatile memory to perform garbage collection, pausing data change operations while allowing passive operations like read and error handling to continue, ensuring efficient bandwidth during the process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If garbage collection is performed without DRAM in storage systems, then cost and device complexity are reduced, but unexpected data modifications occur and performance deteriorates

Engineering Contradiction:
Improvestorage system complexityVSAvoiddata modification consistency
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent segments the garbage collection process into distinct phases: identifying invalid data, pausing data change operations, performing the collection, and resuming operations. This segmentation ensures that data modifications are controlled and predictable, preventing unexpected changes while maintaining system reliability without DRAM

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary actions by pausing data change operations before garbage collection begins and resuming them after completion. This preliminary control mechanism ensures data consistency throughout the garbage collection process, preventing unexpected modifications while maintaining reliability in DRAM-less systems

Inventive Principle:
Principle #10Preliminary action

2Reliability

If garbage collection processes all data in system memory, then data consistency is maintained, but processing time and productivity are reduced

Engineering Contradiction:
Improvedata consistencyVSAvoidgarbage collection throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts and processes only the specific portions of data that require garbage collection rather than processing all data in system memory. By identifying and targeting only invalid or stale data segments, the system maintains data consistency for relevant data while significantly improving garbage collection throughput and productivity

Inventive Principle:
Principle #2Taking out (Extraction)

3Device complexity

If volatile memory size is smaller than memory block size, then device complexity and cost are reduced, but data transfer efficiency worsens

Engineering Contradiction:
Improvememory architecture complexityVSAvoiddata transfer bandwidth
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent introduces a temporal dimension to the data transfer process by implementing multi-pass garbage collection. Instead of requiring all volatile memory to be available simultaneously, the system performs multiple sequential passes, loading and processing data portions in different time stages. This approach maintains data transfer efficiency while working within the constraints of smaller volatile memory size

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20260072609A1System and methods for dram-less garbage collection with improved performance
Publication Date: 2026.03.12 SK HYNIX NAND PRODUCT SOLUTIONS CORP
  • US20260072609A1 patent drawing
  • US20260072609A1 patent drawing
  • US20260072609A1 patent drawing

AI summary

A system and related method, including system memory with a source memory block and a destination memory block each of a memory block size, a first volatile memory and a second volatile memory, each of a volatile memory size. The system includes processing circuitry to receive a garbage collection request associated with the destination memory block. The processing circuitry then determines whether the memory block size is greater than the volatile memory size and pauses data change operations but allows for passive operations to continue. While data change operations are paused the processing circuitry loads a first portion of data of the source memory block to the first volatile memory and a second portion of the data to the second volatile memory. The processing circuitry writes each portion of data from the volatile memory to the destination memory block to complete garbage collection and unpauses the data change operations.