DRAM Address Mapping Analysis for Rowhammer Threat Evaluation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The suppliers of semiconductor devices do not provide the address mapping relationship of DRAM physical addresses, leading to inaccurate and unstable parsing of DRAM-related problems due to interference from cache and system tools like DRAMA and DRAMDig.
Innovation Solution
A method and apparatus for determining an address mapping relationship by obtaining a mapping relationship table between preset addresses and DRAM physical addresses and analyzing bit addresses according to a preset rule to determine attributes, which represent address fields of the DRAM physical addresses, facilitating accurate analysis and troubleshooting of DRAM issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If tools like DRAMA and DRAMDig are used to analyze DRAM physical address information, then analysis capability is provided, but accuracy and stability deteriorate due to cache and system interference
Solution Approach 1:
The patent extracts the DRAM physical address information from the complex system environment by directly reading memory training data and address mapping tables, separating the essential address composition information from cache and system interference. This extraction approach obtains pure address mapping relationships without contamination from other system components.
Solution Approach 2:
The patent performs preliminary actions by obtaining address mapping relationships during memory training phase before normal system operation begins. The mapping tables are established in advance, allowing subsequent address analysis to proceed without interference from runtime cache effects or system variations.
2Reliability
If address mapping relationship is not provided by suppliers, then security is maintained, but problem analysis and solution capability deteriorates
Solution Approach 1:
The patent enables self-service by allowing users to independently obtain and analyze address mapping relationships through memory training data and standardized protocols. Instead of requiring supplier-provided documentation, the system extracts necessary information autonomously from existing memory operations and training sequences.
Solution Approach 2:
The patent introduces mapping relationship tables as intermediaries between the DRAM physical addresses and their compositional meaning. These tables serve as a bridge that translates opaque physical addresses into interpretable address field compositions without requiring suppliers to expose internal address structures.
3Ease of operation
If conventional analysis tools are used, then analysis function is provided, but stability deteriorates due to system interference
Solution Approach 1:
The patent performs preliminary actions by obtaining address mapping relationships during memory training phase before normal system operation begins. The mapping tables are established in advance, allowing subsequent address analysis to proceed without interference from runtime cache effects or system variations.
Solution Approach 2:
The patent uses disposable test patterns and training sequences that are executed temporarily to extract address mapping information. These short-lived test objects are designed to be executed once for information extraction, then discarded, avoiding persistent interference from cache or system state.
Data Source
AI summary
The present disclosure relates to the technical field of semiconductors, and provides a method and an apparatus for determining an address mapping relationship, and a storage medium. The method for determining an address mapping relationship includes: obtaining a mapping relationship table between preset addresses and DRAM physical addresses under a preset condition; and analyzing values of bit addresses in the DRAM physical address according to a first preset rule, to determine an attribute of each bit address in the DRAM physical address, where the attribute is used for representing an address field of the DRAM physical address.