DRAM Bank-Pointer Control Circuit for Power Savings
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Solution Overview
Problem
As signal processing rates increase in memory devices, they consume more power due to frequent clock pulses and transitions, which is inefficient and costly, necessitating a solution to reduce power consumption while maintaining or improving performance.
Innovation Solution
The implementation of a bank-pointer control circuit that uses pointers to manage and route data within memory devices, reducing the need for clock signal transitions by allowing data to flow consecutively without clock signals until a new command or different bank group is accessed, thereby minimizing power consumption and enhancing communication speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If signal processing rates are increased to improve communication speed, then data transfer rate is improved, but power consumption increases due to frequent clock pulses and transitions
Solution Approach 1:
The patent implements a pseudo-flow-through scheme where data flows continuously through the memory device without requiring clock pulses to transition between banks. Data remains on bit lines and travels continuously through sense amplifiers and I/O circuits, eliminating the need for periodic clock-driven transitions while maintaining high data transfer rates
Solution Approach 2:
The patent extracts and eliminates the clock signal mechanism from the data transfer path. By removing the dependency on clock pulses for data transitions between banks, the design achieves high-speed data transfer without the power consumption associated with frequent clock signal generation and distribution
2Adaptability or versatility
If clock signal transitions are increased to manage data routing between banks, then data access flexibility is improved, but power consumption increases
Solution Approach 1:
The patent introduces a bank pointer mechanism as an intermediary that tracks and manages data location across banks without requiring active clock-driven transitions. The bank pointer provides the necessary adaptability for flexible data access by indicating which bank currently holds data, while the actual data movement occurs passively through the continuous flow path without clock intervention
Solution Approach 2:
Data maintains continuous flow through the memory system without interruption from clock cycles. The bank pointer enables flexible access to different banks while data itself flows continuously through the established path, separating the control function (bank selection via pointer) from the data transmission function (continuous flow)
3Reliability
If traditional clock-driven data transfer is used to ensure reliable data routing, then data integrity is maintained, but manufacturing complexity and cost increase
Solution Approach 1:
The patent removes the clock signal distribution network and associated timing control circuitry from the system. This extraction of the clock mechanism simplifies the device architecture by eliminating numerous clock buffers, distribution lines, and timing synchronization circuits, thereby reducing manufacturing complexity and cost while maintaining data integrity through the pseudo-flow-through mechanism
Data Source
AI summary
A dynamic random-access memory (DRAM) device includes memory banks configured to store data and provide access to the stored data; and a data control circuit coupled to the memory banks, the data control circuit configured to: determine a pointer based on a received command, wherein the pointer corresponds to a target memory bank associated with the received command, and route a set of bits to or from the target memory bank using the pointer. In the long burst length and page mode operations where the array access is targeted in certain Bank Group, the pointer is generated and then allow the groups of data bits flowing through the center freely. This pseudo flow through scheme is low power and fast speed by removing the control of gating commands at each stage of the data path during Read and Write operations.