DRAM Bias Contact Point Structures for Bulk Voltage Balance
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Solution Overview
Problem
In dynamic random access memory (DRAM), the large distance between bias voltage supply points affects the bulk bias voltage of MOS transistors, leading to errors in sense amplifier performance and reduced overall amplification capability due to varying bulk bias voltages across different positions.
Innovation Solution
The memory structure includes bias contact point structures disposed between read-write conversion circuits, ensuring equal distances between sense amplification circuits and bias contact point structures, which balances bulk bias voltages and reduces substrate resistance, thereby stabilizing the DRAM performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If bias voltage supply points are located on two sides of read-write conversion circuits, then the structure is simple, but the distance between adjacent bias voltage supply points is large, resulting in large error of bulk bias voltage for MOS transistors in middle region
Solution Approach 1:
The patent divides the bias voltage supply into multiple separate bias contact point structures distributed at different positions (first, second, and third positions) rather than using two centralized supply points. This segmentation allows each MOS transistor region to have its own nearby bias voltage source, reducing the distance and resulting voltage error while maintaining structural simplicity.
2Device complexity
If bias voltage supply points are located on two sides of read-write conversion circuits, then the layout is simple, but MOS transistors in middle region have large distance to bias voltage supply points, affecting amplification capability
Solution Approach 1:
The patent applies local quality by providing different bias voltage supply configurations for different regions. Specifically, it introduces a third bias contact point structure at a position between the first and second bias contact point structures, creating a more densely distributed bias voltage supply network in the middle region where MOS transistors are located. This local enhancement ensures each MOS transistor has minimal distance to its bias voltage source, improving amplification capability while keeping the overall layout simple.
3Ease of operation
If read-write conversion circuits are disposed between memory arrays, then data readout is enabled, but bulk bias voltages at different positions vary, reducing DRAM performance
Solution Approach 1:
The patent implements equipotentiality by ensuring that all MOS transistors in different regions (edge and middle) experience substantially the same bulk bias voltage. This is achieved by distributing multiple bias contact point structures throughout the memory array regions, allowing voltage to be supplied equipotentially to all transistor regions regardless of their position, thereby eliminating performance variations while maintaining data readout functionality.
Data Source
AI summary
Embodiments of the present application provide a memory structure and a memory layout. The memory structure includes: memory arrays, each including a plurality of memory cells; read-write conversion circuits, each disposed between two adjacent ones of the memory arrays in a first direction, being arranged in a second direction, having a symmetry axis in the second direction, and configured to write external data into the memory cells, or read data from the memory cells, and the first direction being perpendicular to the second direction; sense amplification circuits, symmetrically disposed between two adjacent ones of the memory arrays based on the symmetry axis, coupled to the memory cells in the adjacent ones of the memory arrays; and bias contact point structures, disposed in gaps between the read-write conversion circuits, and configured to set a bias voltage of a well region where the bias contact point structures are located.