DRAM Bit Line Contact Overlap for Short Circuit Prevention

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Solution Overview

Problem

Existing DRAM cells with buried gates face defects due to limitations in fabrication technologies, leading to performance and reliability issues.

Innovation Solution

A dynamic random access memory (DRAM) design featuring bit line contacts with sidewalls parallel to active areas, completely overlapping or extending from them, to prevent current turning on between storage node contacts and bit line contacts, thus avoiding short circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the bit line contact is designed to completely overlap or extend from the active area, then short circuit prevention is improved, but the layout area increases

Engineering Contradiction:
Improveshort circuit preventionVSAvoidlayout area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The bit line contact is designed with a specific geometric configuration where its projection completely overlaps or extends from the active area in the planar view. This dimensional arrangement ensures that the contact reaches the necessary regions to prevent short circuits between storage node contacts and bit line contacts, while maintaining fabrication feasibility through proper alignment with the active area geometry.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If fabrication technology is advanced to reduce defects, then manufacturing precision is improved, but fabrication complexity and cost increase

Engineering Contradiction:
Improvedefect reductionVSAvoidfabrication complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The bit line contact is designed with predetermined geometric characteristics (complete overlap or extension from active area) that are established during the fabrication planning stage. This preliminary design ensures that subsequent fabrication processes can proceed with standard techniques while achieving the desired defect reduction and reliability improvement, avoiding the need for complex post-fabrication adjustments.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10068907B1Dynamic random access memory
Publication Date: 2018.09.04 UNITED MICROELECTRONICS CORP
  • US10068907B1 patent drawing
  • US10068907B1 patent drawing
  • US10068907B1 patent drawing

AI summary

A dynamic random access memory (DRAM) includes a substrate, two buried word lines and a bit line contact. The substrate includes a first active area, wherein the first active area extends along a first direction. The buried word lines are disposed in the substrate and across the first active area, wherein the buried word lines extend along a second direction. The bit line contact is disposed on the substrate and overlaps the first active area between the two buried word lines, wherein the bit line contact is enclosed by a first side, a second side, a third side and a fourth side, and the first side is parallel to the third side along a third direction while the second side is parallel to the fourth side along a fourth direction, wherein the third direction is parallel to the first direction and the fourth direction is parallel to the second direction.