DRAM Current-Leakage Bitline Detection Method
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Solution Overview
Problem
Current yield testing methods for Dynamic Random Access Memory (DRAM) manufacturing are unable to accurately detect current-leakage bitlines, leading to low product yield due to incomplete detection of short circuits and structural issues.
Innovation Solution
A memory detection method involving writing and reading data through a series of bitlines and wordlines, using complementary bitlines and sense amplifiers to identify current-leakage bitlines by differentiating between initial and secondary data, and incorporating a preset time to distinguish between complete and incomplete short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing yield testing methods are used, then the manufacturing process is simple, but current-leakage bitlines cannot be accurately detected resulting in low product yield
Solution Approach 1:
The patent segments the bitline detection process into multiple phases: precharging phase, reading phase with first memory data, and reading phase with second memory data. By dividing the detection into discrete steps with different data patterns, the method can identify current-leakage bitlines that would be indistinguishable in a single-pass test, thereby improving detection accuracy and product yield.
Solution Approach 2:
The patent applies preliminary action by precharging the bitline to a specific voltage level before performing the reading operation. This precharging step ensures that the bitline is in a known state, allowing subsequent reading operations to accurately detect current leakage. The method also preliminarily sets up complementary bitlines and sense amplifiers to create optimal detection conditions before actual testing begins.
2Measurement precision
If conventional reading operations are performed without voltage level control, then the operation is simple, but complete and incomplete short circuits cannot be differentiated
Solution Approach 1:
The patent employs dynamics by dynamically controlling the voltage levels of power lines during the reading operation. Specifically, the method gates the power line providing low potential voltage for a preset time period, then gates the power line providing high potential voltage. This dynamic voltage control allows the system to differentiate between complete short circuits (where voltage cannot change) and incomplete short circuits (where voltage can partially change), enabling precise classification of defect types.
Solution Approach 2:
The patent changes the voltage parameter of the bitline by gating power lines providing different potential voltages at different time periods. By switching between low and high potential states and measuring the bitline's response, the method can distinguish between different types of short circuits based on voltage change characteristics, thereby improving detection precision without requiring overly complex circuitry.
3Measurement precision
If bitline level is not controlled before reading, then the detection process is fast, but current leakage cannot be accurately identified
Solution Approach 1:
The patent applies preliminary action by precharging the bitline to a specific voltage level before the actual reading operation. This precharging step, though it adds some time, ensures that the bitline is in a known state, allowing subsequent reading operations to accurately detect current leakage. The method also preliminarily sets up complementary bitlines and sense amplifiers to create optimal detection conditions before actual testing begins.
Solution Approach 2:
The patent maintains continuity of useful action by performing multiple reading operations with different memory data patterns without fully discharging or resetting the bitline between tests. The preset time period allows the bitline to naturally discharge through any leakage paths, and the continuous sequence of write-read operations with complementary data patterns enables efficient detection while minimizing idle time, thus balancing accuracy with speed.
Data Source
AI summary
Embodiments of the present disclosure provide a memory detection method and detection apparatus, for detecting a current-leakage bitline. The method includes: a memory including a plurality of memory cells, a plurality of sense amplifiers, and the sense amplifier including a power line providing a low potential voltage and a power line providing a high potential voltage; writing first memory data to each of the memory cells; performing a reading operation after the first memory data is written; acquiring a first test result based on a difference between first real data and the first memory data; performing the reading operation again to read second real data in each of the memory cells; acquiring a second test result based on a difference between the second real data and second memory data; and acquiring a specific position of the current-leakage bitline based on the second test result and the first test result.