DRAM Bit Line Spacer and Storage Node Contact Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increase in DRAM cell density is limited by high parasitic capacitance due to nitride films used for bit line spacers, and conventional processes for forming storage node contacts result in increased contact resistance and leakage current.
Innovation Solution
A semiconductor device with a bit line spacer formed using an oxide film to reduce parasitic capacitance, and storage node contacts with polysilicon plugs of varying concentrations to minimize leakage current, along with a specific etch-back process to protect the polysilicon layer and secure patterning margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If nitride film is used for bit line spacer to protect sidewalls, then sidewall protection is improved, but parasitic capacitance increases due to high dielectric constant
Solution Approach 1:
The patent changes the material parameter of the spacer from nitride film (high dielectric constant) to oxide film (low dielectric constant). This parameter change maintains the protective function while reducing parasitic capacitance, as oxide materials have inherently lower dielectric constants compared to nitride materials.
Solution Approach 2:
The patent employs a sacrificial oxide layer that is temporarily formed during fabrication and then selectively removed. This disposable oxide layer protects the bit line sidewalls during processing but is ultimately discarded, avoiding the need for permanent high-k materials that would increase parasitic capacitance.
2Ease of manufacture
If conventional damascene process is used to form bit line, then bit line formation is achieved, but polysilicon of storage node contact plug is etched during tungsten etch-back
Solution Approach 1:
The patent introduces an intermediary protective oxide layer that is formed on the storage node contact plug before the tungsten etch-back process. This oxide layer acts as a mediator that protects the polysilicon from etching while allowing the tungsten bit line to be properly formed through the damascene process.
Solution Approach 2:
The patent performs preliminary oxidation to form a protective oxide layer on the storage node contact plug before conducting the tungsten etch-back process. This preliminary action ensures that the polysilicon is protected from unintended etching during subsequent processing steps.
3Reliability
If storage node contact hole is etched with overlay process, then contact resistance is decreased, but patterning margin is reduced
Solution Approach 1:
The patent uses the bit line pattern as a template or copy to define the storage node contact positions. By aligning the storage node contacts with the bit line pattern, the method ensures proper positioning without requiring additional overlay steps, thereby maintaining patterning margins while achieving low contact resistance.
Solution Approach 2:
The storage node contact holes are self-aligned to the bit line pattern through the fabrication process flow. This self-service approach eliminates the need for separate overlay alignment steps, reducing the risk of misalignment and maintaining adequate patterning margins while ensuring proper contact formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance and leakage current, enhancing the density and productivity of DRAM cells by using an oxide film spacer and polysilicon plugs with different dopant concentrations, while maintaining patterning integrity.
Implementation Method 1
since the nitride film has a high dielectric constant, a parasitic capacitance is increased in the bit line
Implementation Method 2
a storage node contact plug formed with polysilicon having a different concentration, thereby reducing leakage current
Data Source
AI summary
A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line hole disposed over the top portion of the semiconductor substrate; an oxide film disposed at sidewalls of the bit line hole; and a bit line conductive layer buried in the bit line hole including the oxide film. A bit line spacer is formed with an oxide film, thereby reducing a parasitic capacitance. A storage node contact is formed to have a line type, thereby securing a patterning margin. A storage node contact plug is formed with polysilicon having a different concentration, thereby reducing leakage current.