DRAM Bit Line Isolation via Spacer and Dielectric Liner
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Solution Overview
Problem
The scaling down of dynamic random access memory (DRAM) elements poses challenges such as short-circuits due to bit line contact with capacitor contact, and existing fabrication methods damage the upper bit line structure using etchants like phosphoric acid, necessitating an improved method to prevent damage and ensure proper integration.
Innovation Solution
A semiconductor memory structure is formed by creating a hard mask layer, forming contact openings, embedding word lines in the semiconductor substrate, and using spacers to isolate the bit line from the capacitor contact, with a dielectric liner on the bit line sidewalls, allowing for perpendicular orientations and reducing the need for phosphoric acid etching, thus preventing damage and enhancing integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phosphoric acid etching is used to pattern nitride for preventing short-circuit, then isolation between bit line contact and capacitor contact is improved, but the upper bit line structure is damaged
Solution Approach 1:
The patent extracts and removes the harmful phosphoric acid etching step from the fabrication process. Instead of using phosphoric acid to pattern nitride, the invention uses alternative materials (such as oxygen plasma treatment) that achieve the same isolation function without damaging the bit line structure.
Solution Approach 2:
The patent introduces an intermediary material or process step between the nitride layer and the phosphoric acid etchant. This intermediary serves as a protective layer or alternative etching medium that enables pattern formation without the harmful effects of phosphoric acid on the bit line structure.
2Quantity of substance
If element size is scaled down to increase density, then integration density is improved, but short-circuit risk between bit line contact and capacitor contact increases
Solution Approach 1:
The patent addresses the short-circuit risk by introducing vertical isolation structures (such as spacer layers and dielectric liners) that create separation in the vertical dimension. This dimensional approach allows closer horizontal spacing of elements while maintaining reliable electrical isolation through vertical barriers.
Solution Approach 2:
The patent segments the isolation function into multiple distinct layers and structures (nitride layer, spacer, dielectric liner, cap layer) rather than relying on a single isolation mechanism. This segmentation allows each layer to perform a specific isolation function, collectively preventing short-circuits while enabling higher density.
3Reliability
If multiple isolation layers and spacers are added to prevent short-circuit, then reliability is improved, but fabrication process complexity increases
Solution Approach 1:
The patent merges multiple functions into combined process steps where possible. For example, spacer formation and cap layer deposition are integrated into a unified sequence that achieves both isolation and protection functions simultaneously, reducing the total number of discrete process steps.
Solution Approach 2:
The patent designs the spacer and cap layer structures to serve multiple functions: electrical isolation, physical protection of underlying layers, and definition of contact alignment. This multi-functionality reduces the need for separate dedicated structures, simplifying the overall fabrication process.
Data Source
AI summary
A method for forming a semiconductor memory structure includes providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate; forming a contact opening corresponding to the pair of word lines through the hard mask layer and a portion of the semiconductor substrate; forming a pair of spacers on sidewalls of the contact opening; filling the contact opening with a conductive material to form a contact; forming a bit line directly above the contact and the pair of spacers, and forming a dielectric liner on sidewalls of the bit line. The pair of word lines is embedded in an active region of the semiconductor substrate and extends in a first direction. The bit line extends in a second direction. The first direction is perpendicular to the second direction.