DRAM Buried Gate Layout Design for Leakage Reduction
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Solution Overview
Problem
Current DRAM cell fabrication with buried gates faces defects due to limitations in fabrication technologies, necessitating an improved method to enhance performance and reliability by forming minimized elements with finer line widths and spaces.
Innovation Solution
A method involving a layout design using photomasks to establish opening patterns and a blocking layer, allowing for the formation of a compact semiconductor structure with a core and periphery region, enabling the creation of a DRAM device with a simplified process flow by using optical proximity correction and self-aligned double patterning techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar gate structure is used, then fabrication process is simpler, but current leakage is higher and performance is inferior
Solution Approach 1:
The gate structure is divided into two parts: a planar gate at the top and a buried gate extending beneath the channel. This segmentation allows the device to combine the fabrication simplicity of planar gates with the electrical performance of buried gates, effectively reducing current leakage while maintaining manufacturability
Solution Approach 2:
The buried gate is nested beneath the channel region, extending under the planar gate structure. This nested configuration allows the buried gate to provide additional channel control and reduce leakage currents without adding significant external complexity to the device architecture
2Productivity
If memory cell size is scaled down, then integration level and memory capacity increase, but fabrication defects increase
Solution Approach 1:
The buried gate is formed in the substrate before the planar gate and other memory cell structures are constructed. This preliminary formation of the buried gate establishes a stable foundation that guides subsequent fabrication steps, enabling better control over alignment and dimensions even as cell sizes are scaled down
Solution Approach 2:
The layout design methodology uses self-aligned processes where previously formed structures serve as alignment references for subsequent patterns. This self-alignment mechanism reduces the accumulation of alignment errors during scaling, thereby reducing fabrication defects while maintaining high integration levels
3Manufacturing precision
If optical exposure is used with conventional limits, then exposure process is simpler, but line width and space minimization is restricted
Solution Approach 1:
The layout design introduces a vertical dimension by forming the buried gate beneath the channel rather than only at the surface. This three-dimensional arrangement allows for more compact planar footprints and finer effective line widths without requiring proportional reductions in optical exposure capabilities
Solution Approach 2:
The patent introduces an intermediary layout design methodology that acts as a mediator between optical exposure capabilities and desired feature dimensions. This methodology uses carefully designed pattern arrangements and self-aligned processes to achieve finer features than conventional direct exposure would allow, without requiring complex multi-step lithography
Data Source
AI summary
A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.