DRAM Cache Tag Storage via Error Protection Region Merging
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Solution Overview
Problem
The existing DRAM cache implementations are inefficient in terms of memory usage due to the significant space dedicated to tag storage, which reduces the effective capacity for storing data, and conventional error correction codes consume more space than necessary.
Innovation Solution
Implementing a DRAM cache management circuit that uses an error detection code (EDC) instead of an error correcting code (ECC) and stores the tag and EDC in the error protection region, allowing for reduced or eliminated tag storage regions, thereby increasing memory capacity while maintaining error detection capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a separate tag storage region is provided in each cache entry, then tag storage is simplified and direct, but the effective memory capacity for data storage is reduced
Solution Approach 1:
The patent merges the tag storage function with the error protection region by storing tags in the same memory locations where error protection codes are normally stored. This consolidation eliminates the need for separate tag storage regions, thereby increasing effective memory capacity while maintaining tag accessibility through the error protection infrastructure.
Solution Approach 2:
The error protection region is given multiple functions: it continues to provide error detection and correction capabilities while simultaneously serving as storage for cache tags. This multi-functional use of the error protection region maximizes memory utilization without sacrificing reliability or tag management capabilities.
2Reliability
If conventional ECC is used for error protection, then data integrity is maintained with correction capability, but more memory space is consumed than necessary
Solution Approach 1:
The patent changes the error protection parameter from full ECC (which provides correction) to EDC (which provides only detection). This parameter change reduces the number of bits required for error protection from typically 8-10 bits down to 4-6 bits, freeing up memory space for tag storage while maintaining sufficient reliability for the cache application where detection is often adequate.
Solution Approach 2:
The patent uses a simpler, less resource-intensive error detection code instead of the more complex and space-consuming error correcting code. This approach accepts that some errors may go undetected or require refresh operations, trading perfect reliability for improved space efficiency, which is acceptable for cache memory where data is frequently accessed and refreshed.
Data Source
AI summary
Providing space-efficient storage for dynamic random access memory (DRAM) cache tags is provided. In one aspect, a DRAM cache management circuit provides a plurality of cache entries, each of which contains a tag storage region, a data storage region, and an error protection region. The DRAM cache management circuit is configured to store data to be cached in the data storage region of each cache entry. The DRAM cache management circuit is also configured to use an error detection code (EDC) instead of an error correcting code (ECC), and to store a tag and the EDC for each cache entry in the error protection region of the cache entry. In this manner, the capacity of a DRAM cache can be increased by avoiding the need for the tag storage region for each cache entry, while still providing error detection for the cache entry.