DRAM Node Contact Spacer Cap Layer Seam Sealing
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Solution Overview
Problem
As dynamic random access memory (DRAM) designs shrink, it becomes challenging to fill materials into openings without forming seams and abnormal bridging during conductor filling, which can lead to electrical issues.
Innovation Solution
The implementation of a manufacturing method for DRAM that involves forming spacers with a cap layer to seal seams between node contacts, preventing conductor bridging by exposing and sealing these seams with a cap layer during the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conductor filling is performed into openings in shrunk DRAM designs, then device integration is improved, but seams and abnormal bridging are formed
Solution Approach 1:
The patent applies preliminary action by forming a cap layer within the seam before conductor filling occurs. This preemptive measure seals the seam to prevent conductor material from entering and causing bridging, while still allowing the conductor filling process to proceed for device integration
Solution Approach 2:
The cap layer acts as an intermediary element between the seam and the conductor material. It selectively blocks conductor filling in the seam region while permitting conductor deposition in the intended contact regions, thus mediating between the competing requirements of integration and precision
2Reliability
If spacer materials are filled between node contacts, then node contacts are separated, but seams are formed in the spacer materials
Solution Approach 1:
The cap layer is formed in the seam before subsequent conductor filling steps. This preliminary sealing action prevents the seam from causing bridging issues later in the process, while the spacer material continues to provide node contact separation
Solution Approach 2:
The cap layer is selectively placed only in the seam regions of the spacer materials, leaving the rest of the spacer structure intact. This local modification maintains the separation function while eliminating the harmful seam effect in specific locations
3Ease of manufacture
If etching is performed on bit line structure, then processing is completed, but middle liner is damaged
Solution Approach 1:
The cap layer serves as a protective cushioning layer that is formed beforehand to prevent etchant from damaging the middle liner during bit line structure processing. It absorbs the harmful effect of the etching process
Data Source
AI summary
Provided are a dynamic random access memory and a method for manufacturing the same. The DRAM includes: a plurality of word line structures, located in a substrate; a plurality of bit line structures, located above the substrate, crossing over the plurality of word line structures; a plurality of node contacts, each of which being located between adjacent two of the word line structures and adjacent two of the bit line structures; and a plurality of first spacers, separating the plurality of node contacts. Each of the plurality of first spacers further comprises: spacer material, filled in a gap between the node contacts that are adjacent; and a first cap layer, embedded in the spacer material.