DRAM Capacitor Electrode Deposition via CVD and ALD
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Solution Overview
Problem
In the miniaturization of integrated circuits, capacitors in DRAMs face challenges in storing sufficient charge due to limited chip area, with traditional roughened polysilicon electrodes leading to dopant diffusion issues and impurity incorporation in conductive overcoats like titanium nitride, affecting transistor characteristics and capacitance.
Innovation Solution
A method involving the deposition of electrically conductive layers using a combination of chemical vapor deposition (CVD) and atomic layer deposition (ALD) techniques, where a first conductive layer is formed by reacting gaseous precursors at a high rate, followed by a second conductive layer deposited at a slower rate with lower impurity content and smoother surface roughness, to create a nanolayer reaction product, reducing dopant diffusion and enhancing capacitance without significant area increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If roughened polysilicon is used as bottom electrode to increase capacitance, then electrode surface area increases, but dopant diffusion to substrate occurs
Solution Approach 1:
A nitrogen-containing dielectric layer is introduced as an intermediary barrier between the roughened polysilicon bottom electrode and the silicon substrate. This dielectric layer prevents dopant diffusion from the electrode to the substrate while maintaining the high surface area of the roughened electrode structure for increased capacitance.
Solution Approach 2:
The invention changes the material parameter of the interface between electrode and substrate by replacing direct silicon-silicon contact with a dielectric layer. This parameter change (from conductive to insulating material) eliminates the dopant diffusion pathway while preserving the electrode's capacitive function.
2Reliability
If titanium nitride overcoat is deposited by CVD to increase conductivity, then electrical conductivity improves, but impurity incorporation occurs
Solution Approach 1:
The deposition method is changed from CVD to ALD, representing a parameter change in the manufacturing process. ALD provides better control over deposition conditions, resulting in titanium nitride films with lower impurity content while maintaining high electrical conductivity and conformal coverage.
Solution Approach 2:
The invention substitutes the CVD chemical deposition mechanism with the ALD atomic-layer deposition mechanism. This substitution allows for more precise control of the deposition process, reducing impurity incorporation while achieving the desired electrical conductivity in the titanium nitride overcoat.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases capacitance by minimizing dopant diffusion and impurity incorporation, maintaining reliable transistor operation while optimizing chip area usage, thereby enhancing the charge storage capacity of DRAM capacitors.
Implementation Method 1
a first conductive layer is formed by reacting gaseous precursors at a high rate
Implementation Method 2
depositing a second conductive layer at a slower rate with lower impurity content and smoother surface roughness by depositing a precursor layer of gaseous precursors and reacting the precursor layer with a second gaseous precursor to form a nanolayer reaction product
Data Source
AI summary
The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 Å.