DRAM Capacitor Electrode Design for High Density
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Solution Overview
Problem
Conventional DRAM with concave-type capacitance electrodes face challenges in maintaining required capacitance as cell size decreases, due to smaller capacitor opening portions reducing storable memory charge and necessitating larger mis-alignment margins that increase cell size.
Innovation Solution
A semiconductor memory device configuration where the upper electrode is formed only over the bottom and sides of the capacitor opening portion, eliminating the need for mis-alignment margin a2, and extending upper electrodes over the interlayer insulating film to connect adjacent electrodes, thereby increasing capacitance without increasing cell size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the cell size is reduced to increase integrating density, then the capacitor opening portion area decreases, but the storable memory charge decreases
Solution Approach 1:
The capacitance electrode is designed with a recessed structure where the upper surface is lower than the surrounding interlayer insulating film surface. This vertical dimensionality change allows the capacitor opening portion to extend deeper, increasing the effective capacitance area and storable charge without increasing the planar cell footprint, thus resolving the contradiction between integrating density and storable memory charge.
2Length of moving object
If the capacitor opening portion area is reduced to decrease cell size, then the mis-alignment margin requirement becomes larger relative to cell size, but the available area for capacitance is reduced
Solution Approach 1:
By creating a recessed capacitance electrode structure, the patent utilizes the vertical dimension to provide additional mis-alignment tolerance. The recessed design allows the capacitor opening portion to be positioned more flexibly relative to the bit-line contact plug, as the deeper structure provides a larger effective margin zone, reducing the impact of lateral mis-alignment on overall device performance.
3Quantity of substance
If the upper electrode is extended over the interlayer insulating film to connect adjacent electrodes, then the capacitance area increases, but the device complexity increases
Solution Approach 1:
The upper electrode is designed to extend beyond the capacitor opening portion and merge with adjacent upper electrodes through the interlayer insulating film. This merging creates a continuous conductive structure that increases total capacitance while utilizing existing electrode material and processes, thereby minimizing the increase in device complexity.
Data Source
AI summary
A semiconductor memory device has a first interlayer insulating film formed on a semiconductor substrate and having a capacitor opening portion provided in the film, and a capacitance element formed over the bottom and sides of the capacitor opening portion and composed of a lower electrode, a capacitance insulating film, and an upper electrode. A bit-line contact plug is formed through the first interlayer insulating film. At least parts of respective upper edges of the lower electrode, the capacitance insulating film, and the upper electrode at a side facing the bit-line contact plug are located below the surface of the first interlayer insulating film, the lower electrode, the capacitance insulating film, and the upper electrode being located over the sides of the capacitor opening portion. The upper electrode is formed over only the bottom and sides of the capacitor opening portion.