DRAM Memory Cell Bit Line Noise Coupling Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices shrink, adjacent bit lines in DRAM cells experience undesirable coupling effects, leading to noise interference and incorrect data determination due to reduced distances between them.
Innovation Solution
The memory array is designed with memory cells comprising a first and second switch device and a capacitor, where memory cells are grouped such that only one group's bit lines transmit data at a time, minimizing noise coupling by ensuring adjacent bit lines are not from the same group.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the size of semiconductor devices is shrunk to reduce distances between bit lines, then the area of the memory device is reduced, but noise coupling between adjacent bit lines increases
Solution Approach 1:
The memory array is divided into multiple banks, and within each bank, bit lines are grouped into sets where adjacent bit lines belong to different groups. This segmentation allows independent control of different bit line groups through separate select lines, enabling noise reduction by deactivating select lines for inactive groups while maintaining the compact layout.
Solution Approach 2:
The patent implements dynamic control of bit line groups by activating only the select lines corresponding to currently active bit line groups. This dynamic switching allows the system to adaptively manage noise coupling by deactivating select lines for inactive groups during read/write operations, reducing capacitive coupling effects without requiring increased physical spacing.
2Quantity of substance
If the distance between adjacent bit lines is reduced, then the integration density is improved, but data transmission accuracy deteriorates due to noise interference
Solution Approach 1:
Bit lines are segmented into multiple groups with associated select lines, allowing independent control. This segmentation enables the system to activate only the necessary bit line groups for current operations, isolating active signal paths from inactive ones and reducing noise interference while maintaining high integration density.
Solution Approach 2:
Select lines act as intermediaries between control logic and bit lines. By controlling the activation state of select lines, the system can mediate the coupling effect between adjacent bit lines, allowing high-density layout while maintaining data transmission accuracy through selective isolation of inactive bit line groups.
3Area of stationary object
If memory cells are arranged in a compact matrix, then the area is reduced, but noise coupling between adjacent bit lines increases
Solution Approach 1:
The compact memory array is segmented into banks and bit line groups with hierarchical select line control. This segmentation allows the maintain compact area while reducing noise coupling by deactivating select lines for inactive groups, creating electrical isolation without increasing physical spacing.
Solution Approach 2:
The patent employs dynamic control where only the select lines corresponding to currently active bit line groups are enabled. This dynamic approach allows the compact memory array to operate with reduced noise coupling by adaptively isolating inactive bit line groups during read/write operations, maintaining high density without sacrificing noise performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This arrangement effectively reduces noise coupling between bit lines, allowing for accurate data transmission while potentially downsizing the circuit region and enabling the use of a 3D structure.
Implementation Method 1
The capacitor is utilized to store data when it is charged or discharged (logic value 0 or 1)
Implementation Method 2
The switch device is turned on or off via a word line
Implementation Method 3
adjacent bit lines may suffer an undesirable coupling effect and generate noise to each other
Data Source
AI summary
A memory cell (100) having a first switch device (Tr1), a second switch device (Tr2) and a capacitor (C) is disclosed. The first switch device (Tr1) has a control terminal coupled to and controlled by a select line (SL), a first terminal coupled to a bit line (BL), and a second terminal. The second switch device (Tr2) has a first terminal coupled to the second terminal of the first switch device (Tr1), a control terminal coupled to and controlled by a word line (WL), and a second terminal. The capacitor (C) has a first terminal coupled to the second terminal of the second switch device (Tr2) and a second terminal coupled to a predetermined voltage level, wherein data is read from the capacitor (C) or written to the capacitor (C) via the bit line (BL).