DRAM Cell Layout Area Reduction via Vertical Channel
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Solution Overview
Problem
Current dynamic random access memory (DRAM) cells face limitations in reducing layout area due to the requirement of a single pillar per cell transistor, which restricts further miniaturization.
Innovation Solution
A DRAM cell design featuring a cell transistor with a transmission channel formed on a facing bar of constant width and height, where one side is connected to a bit line plug and the other side to a storage, allowing for reduced layout area by sharing components and optimizing channel formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If a single pillar per DRAM cell is used, then the transmission channel length can be maintained, but the layout area cannot be reduced further
Solution Approach 1:
The patent transitions from a planar transmission channel to a vertical transmission channel by forming the channel along the side surface of a pillar structure. This dimensional change allows the transmission channel to extend in the vertical direction (depth) rather than only in the horizontal plane, thereby maintaining adequate channel length while reducing the horizontal layout area occupied by each DRAM cell.
Solution Approach 2:
The patent embeds the transmission channel within the vertical structure of the pillar, nesting the channel formation inside the three-dimensional space defined by the pillar's side surface. This nesting approach allows multiple functional elements to share the same vertical space, reducing the overall footprint of the DRAM cell while preserving the necessary channel dimensions.
2Area of stationary object
If the layout area is reduced, then integration density increases, but the transmission channel length may be compromised
Solution Approach 1:
By forming the transmission channel along the vertical side surface of the pillar rather than in the horizontal plane, the patent extends the channel length in the vertical dimension. This allows the horizontal footprint to be minimized for higher integration density while the vertical extent provides sufficient channel length for proper transistor operation.
3Length of stationary object
If vertical-type pillar structure is used, then transmission channel length is secured in limited area, but device complexity increases
Solution Approach 1:
The patent divides the DRAM cell structure into distinct functional segments: the pillar structure serves as the vertical framework, the side surface provides the transmission channel region, and the gate electrode wraps around to control the channel. This segmentation allows each component to be optimized independently while maintaining overall simplicity through modular construction.
Solution Approach 2:
The pillar structure serves multiple functions simultaneously: it provides mechanical support, defines the vertical boundary for the transmission channel, and serves as the substrate for gate electrode formation. This multi-functionality reduces the need for separate structural elements, thereby managing device complexity while achieving the desired channel length.
Data Source
AI summary
The fabricating method of a DRAM cell includes forming a facing bar that extends in a direction of the word line; forming a gate of the cell transistor on one side surface of the facing bar; forming a bit line plug that is electrically connected to one side of the transmission channel, which is formed on the one side surface of the facing bar; and forming the storage that is electrically connected to the other side of the transmission channel, which is formed on the horizontal surface of the semiconductor substrate. A pair of DRAM cells shares a facing bar and a bit line plug. In accordance with the present disclosure, a required layout area is significantly reduced.