DRAM Chip Sparing Data Corruption Avoidance
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Solution Overview
Problem
In computer memory systems with chip sparing, data corruption occurs due to the overlap of chip sparing transactions with other memory transactions, leading to performance degradation or corruption, as existing methods either halt all transactions or allow mixed transactions, which can result in data inconsistencies.
Innovation Solution
A memory controller system that performs sparing transactions by reading and writing data from one memory chip to another while allowing additional memory transactions between the start and end of the sparing process, unless targeted at the same location, and allows transactions for a configurable period after writing to prevent data corruption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If other memory transactions are stopped during chip sparing operation, then data corruption is prevented, but system performance deteriorates due to the significant time required for sparing operations
Solution Approach 1:
The patent applies local quality by differentiating transaction handling based on target location: transactions to locations being spared are blocked, while transactions to other locations are permitted. This selective approach maintains data integrity for spared locations while preserving system performance for non-affected operations.
Solution Approach 2:
The patent segments the memory address space into locations being spared and other locations, applying different transaction policies to each segment. This allows concurrent processing of non-conflicting transactions while protecting the sparing operation's data integrity.
2Productivity
If a non-sparing memory write occurs between read and write of chip sparing read/write pair to the same location, then system performance is maintained, but data corruption occurs because the sparing write may overwrite the non-sparing write
Solution Approach 1:
The patent applies preliminary anti-action by preemptively blocking new write transactions to locations that are currently being spared, before the corruption can occur. This prevents the race condition where a non-sparing write might be overwritten by the sparing write operation.
Solution Approach 2:
The patent establishes a blocking mechanism in advance for locations undergoing sparing operations, ensuring that no conflicting writes can occur during the critical window between read and write operations.
3Productivity
If non-sparing memory transactions are allowed during chip sparing operation, then system performance is maintained, but data may be written to both the given location and corresponding spared location causing corruption
Solution Approach 1:
The patent applies local quality by implementing location-specific transaction blocking: only writes to the specific location being spared are blocked, while writes to other locations continue normally. This prevents duplicate writes to spared locations while maintaining overall system performance.
4Productivity
If chip sparing operation is performed quickly, then system performance is maintained, but data corruption risk increases due to insufficient time for proper error correction and verification
Solution Approach 1:
The patent introduces a configurable delay period as an intermediary between the sparing write operation and the next sparing transaction. This delay ensures proper settling and verification time while allowing non-critical transactions to proceed, balancing speed and reliability.
Data Source
AI summary
A memory controller, system, and methods are disclosed. The system comprises a memory controller interconnected to a plurality of memory chips. Each memory chip stores data at a plurality of locations. The memory controller performs a sparing transaction comprising reading data from a given location of one or more of the memory chips including a first memory chip, writing the data to a given location of one or more of the memory chips including a second memory chip, wherein during writing, data from the first memory chip is written to the second memory chip, and allowing additional memory transactions directed to the memory chips between the start of reading and the end of writing unless the additional memory transaction is targeted to the given location. In a further embodiment, the sparing transaction comprises correcting errors in the data before writing the data.