DRAM Cycle Stealing via Expanded Refresh Timing
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Solution Overview
Problem
Conventional DDR DRAM systems restrict other devices from accessing the DDR bus without risking collisions with CPU-originated cycles, limiting flexibility and bandwidth for operations like refresh cycles, which vary by DRAM density and require specific timing.
Innovation Solution
Implementing a cycle stealing mechanism using an external DDR controller or buffer with programmable registers to isolate the DRAM array, allowing an alternate access time by increasing the tRFC value, and using command detection logic to initiate operations during the alternate access time, thereby reserving bandwidth for additional operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the DRAM array is isolated from the host controller during refresh cycles, then bandwidth is reserved for alternate access operations, but the host controller must wait longer than the standard tRFC period
Solution Approach 1:
The system dynamically adjusts the tRFC timing parameter to create an expanded refresh cycle window. By programmatically increasing tRFC beyond the JEDEC standard, the system creates temporal flexibility that allows alternate masters to access the DRAM array during the extended refresh period without conflicting with host controller operations.
Solution Approach 2:
The refresh cycle is segmented into distinct time windows: a first portion reserved for host controller access and a second portion (within the expanded tRFC window) available for alternate masters. This temporal segmentation allows multiple masters to utilize the DRAM array during different phases of the same refresh cycle, effectively increasing overall bandwidth availability.
2Adaptability or versatility
If cycle stealing is implemented to allow additional access during refresh cycles, then flexibility and bandwidth are improved, but the risk of collision with CPU-originated cycles increases
Solution Approach 1:
The memory controller acts as an intermediary that arbitrates access requests from multiple masters. It receives commands from both the host controller and alternate masters, determines timing windows within the expanded tRFC period that are safe for alternate access, and sequences commands to prevent collisions with CPU-originated cycles while maximizing bandwidth utilization.
Solution Approach 2:
The system uses the inherently periodic refresh cycles as self-service opportunities for alternate masters. By identifying and utilizing the time windows created by mandatory refresh operations, the system allows alternate access without requiring dedicated separate cycles, thereby improving flexibility while maintaining reliability through the structured, predictable timing of refresh-based access windows.
Data Source
AI summary
A method for operating a DRAM is provided. The method includes initializing a dynamic random access memory (“DRAM”) array from a host controller, which is coupled to the DRAM array. The method includes isolating the dynamic random access memory array from a host controller and allowing a host computer to wait for a selected time period greater than the tRFC to define an alternate access time. The method includes initiating an access command to the DRAM array during the alternate access time.