DRAM Disturbance-Aware Refresh Scheduling
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Solution Overview
Problem
Dynamic random access memory (DRAM) experiences deterioration in refresh characteristics due to disturbances caused by frequent access to adjacent memory cells, leading to increased leakage current and data loss, particularly as cell spacing decreases with scaling.
Innovation Solution
A method is introduced to monitor and adjust the refresh schedule of memory cells based on a disturbance count value, prioritizing cells with higher disturbance levels for irregular refresh operations to mitigate the impact of adjacent cell interference and maintain data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cell spacing is reduced to increase memory density, then memory capacity increases, but disturbance from adjacent cells increases causing refresh characteristic deterioration
Solution Approach 1:
The patent applies local quality by differentiating refresh operations into regular refresh for most cells and irregular refresh for specifically identified disturbed cells. The disturbance count value mechanism allows the system to treat individual cells with different refresh needs based on their local disturbance conditions, rather than applying uniform refresh to all cells.
Solution Approach 2:
The patent implements dynamics by making the refresh schedule adaptive rather than static. The irregular refresh operation dynamically adjusts the refresh interval for disturbed cells based on real-time disturbance counting, allowing the system to respond to changing access patterns and disturbance levels during operation.
2Speed
If high voltage is applied to word line to enable transistor access, then access capability improves, but leakage current in adjacent cells increases due to pass gate effect
Solution Approach 1:
The patent applies preliminary action by performing irregular refresh operations on disturbed cells before data loss occurs. The disturbance counting mechanism detects potential problems in advance, and the premature refresh prevents leakage current from causing actual data loss, rather than waiting for errors to manifest.
Solution Approach 2:
The patent implements feedback through the disturbance counting mechanism that monitors access patterns and uses this information to adjust refresh scheduling. The system continuously counts disturbances caused by high-voltage word line activations and feeds this information back to determine which cells need irregular refresh, creating a closed-loop control system.
3Productivity
If frequent access to particular address occurs, then productivity increases, but refresh characteristic of cell deteriorates rapidly due to concentrated disturbance
Solution Approach 1:
The patent applies local quality by identifying specific cells that experience concentrated disturbance from repeated access patterns and applying targeted irregular refresh only to those affected cells. The disturbance count value allows differentiation between cells that need frequent refresh versus those that follow regular refresh schedules.
Solution Approach 2:
The patent implements dynamics by making the refresh system adaptive to actual usage patterns. Rather than using a fixed refresh schedule, the system dynamically identifies cells experiencing high disturbance from frequent access and adjusts their refresh timing accordingly, allowing the refresh policy to evolve with workload characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the negative effects of cell interference by scheduling priority refresh operations for cells with high disturbance values, thereby enhancing the refresh characteristics and data reliability of DRAM memory devices.
Implementation Method 1
an electric field generated by the high voltage may decrease a threshold voltage of an access transistor in an adjacent cell
Data Source
AI summary
A memory device, a memory system, and operating methods thereof are provided. The method of operating the memory device, which includes a first memory cell and a second memory cell neighboring the first memory cell, includes counting a disturbance value of the second memory cell each time the first memory cell is accessed, updating a disturbance count value of the second memory cell based on the counting, adjusting a refresh schedule based on the disturbance count value of the second memory cell, a desired threshold and a maximum disturbance count value, and resetting the disturbance count value of the second memory cell and the maximum disturbance count value when the second memory cell is refreshed according to the adjusted refresh schedule.