DRAM Gate Fabrication via Single-Chamber Etch and Deposition
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for transistor gate fabrication involve multiple process steps, including separate reaction chambers for etching and deposition, which slows throughput and increases the risk of errors during substrate transfer.
Innovation Solution
The method involves depositing protective material along the sidewalls of transistor gates in the same reaction chamber used for etching, utilizing reactants suitable for low temperatures, eliminating the need for transferring substrates between chambers and reducing process steps by conducting etching, deposition, and anisotropic etching in a single chamber without breaking vacuum.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate reaction chambers are used for etching and deposition, then each process can be optimized independently, but throughput is reduced and error risk increases during substrate transfer
Solution Approach 1:
The patent combines etching and deposition processes into a single reaction chamber, eliminating the need for substrate transfer between chambers. This integration maintains process reliability while significantly improving throughput by removing transfer steps and associated error risks.
Solution Approach 2:
The reaction chamber is designed to perform multiple functions - both etching and deposition - within the same chamber. This multi-functionality allows the system to maintain optimized processes for each operation while eliminating the need for separate specialized chambers, thereby improving throughput without compromising reliability.
2Reliability
If protective material is deposited before oxidation, then metal-containing layers are protected from oxidation, but additional process steps are required
Solution Approach 1:
The patent applies preliminary action by depositing protective material on metal-containing layers before oxidation occurs. This pre-protection step prevents oxidation damage while the subsequent anisotropic etching selectively removes the protective material from sidewalls, achieving both protection and pattern definition without excessive complexity.
Solution Approach 2:
The protective material is selectively removed through anisotropic etching to expose metal-containing layers only in specific locations (horizontal surfaces) while maintaining protection on sidewalls. This local quality approach ensures oxidation protection where needed while enabling metal exposure where required for circuit functionality.
3Manufacturing precision
If multiple process steps are performed in sequence, then each step can be controlled independently, but the number of steps increases and costs rise
Solution Approach 1:
The patent merges deposition, oxidation, and anisotropic etching into a single integrated process sequence within one reaction chamber. This combination maintains precise control over each step through sequential execution while reducing the overall number of discrete process steps and associated costs compared to conventional separate-chamber approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves throughput, reduces costs, and minimizes errors by integrating deposition and etching steps within a single reaction chamber, enhancing the efficiency of transistor gate fabrication while protecting metal-containing layers from oxidation.
Implementation Method 1
depositing protective material along the sidewalls of transistor gates in the same reaction chamber used for etching, utilizing reactants suitable for low temperatures
Implementation Method 2
conducting etching, deposition, and anisotropic etching in a single chamber
Data Source
AI summary
Some embodiments include methods of forming transistor gates. A gate stack is placed within a reaction chamber and subjected to at least two etches, and to one or more depositions to form a transistor gate. The transistor gate may comprise at least one electrically conductive layer over a semiconductor material-containing layer. At least one of the one or more depositions may form protective material. The protective material may extend entirely across the at least one electrically conductive layer, and only partially across the semiconductor material-containing layer to leave unlined portions of the semiconductor material-containing layer. The unlined portions of the semiconductor material-containing layer may be subsequently oxidized.