DRAM Input Signal Latch Timing Equalization via Buffer Count
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Solution Overview
Problem
In semiconductor devices like DRAM, the unequal distances between input terminals and latch circuits complicate the use of high-speed clock signals due to increased chip area and current consumption caused by detoured interconnects, which are necessary to equalize signal path lengths.
Innovation Solution
The semiconductor device employs a configuration where input signals are latched at different timings, allowing for unequal signal path lengths between input terminals and latch circuits, reducing the need for detoured interconnects and thereby minimizing charge/discharge current generated at signal paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If detoured interconnects are used to equalize signal path lengths, then latch margin is improved, but chip area increases and current consumption grows
Solution Approach 1:
The patent applies local quality by providing different numbers of buffer circuits in different signal paths. Specifically, signal paths with shorter physical lengths receive more buffer circuits to increase delay, while longer paths receive fewer buffers. This local differentiation of buffer quantities compensates for path length variations without requiring detoured interconnects, thus improving latch margin while avoiding area increase.
Solution Approach 2:
The patent changes the parameter of buffer circuit quantity to control signal delay. By adjusting the number of buffers in each path, the overall delay is equalized across all signal paths. This parameter-based approach (changing buffer count rather than physical path length) achieves path equalization without detours, reducing both area and current consumption while maintaining reliability.
2Reliability
If detoured interconnects are used to equalize signal path lengths, then latch margin is improved, but current consumption grows due to charge/discharge through parasitic capacitance
Solution Approach 1:
The patent applies local quality by providing different numbers of buffer circuits in different signal paths. Specifically, signal paths with shorter physical lengths receive more buffer circuits to increase delay, while longer paths receive fewer buffers. This local differentiation of buffer quantities compensates for path length variations without requiring detoured interconnects, thus improving latch margin while avoiding area increase.
Solution Approach 2:
The patent changes the parameter of buffer circuit quantity to control signal delay. By adjusting the number of buffers in each path, the overall delay is equalized across all signal paths. This parameter-based approach (changing buffer count rather than physical path length) achieves path equalization without detours, reducing both area and current consumption while maintaining reliability.
3Area of stationary object
If unequal signal path lengths are used, then chip area is reduced and current consumption decreases, but latch margin becomes smaller
Solution Approach 1:
The patent changes the parameter of buffer circuit quantity to control signal delay. By adjusting the number of buffers in each path, the overall delay is equalized across all signal paths. This parameter-based approach (changing buffer count rather than physical path length) achieves path equalization without detours, reducing both area and current consumption while maintaining reliability.
Solution Approach 2:
The patent introduces buffer circuits as intermediary elements between the input terminals and latch circuits. These buffers act as mediators that can be selectively added or removed in different paths to equalize signal arrival times. This intermediary approach allows flexible delay adjustment without physical path modification, achieving reliable latching with minimal area and power consumption.
4Loss of energy
If unequal signal path lengths are used, then current consumption decreases due to reduced parasitic capacitance, but latch operations become difficult at high clock speeds
Solution Approach 1:
The patent changes the parameter of buffer circuit quantity to control signal delay. By adjusting the number of buffers in each path, the overall delay is equalized across all signal paths. This parameter-based approach (changing buffer count rather than physical path length) achieves path equalization without detours, reducing both area and current consumption while maintaining reliability.
Solution Approach 2:
The patent introduces buffer circuits as intermediary elements between the input terminals and latch circuits. These buffers act as mediators that can be selectively added or removed in different paths to equalize signal arrival times. This intermediary approach allows flexible delay adjustment without physical path modification, achieving reliable latching with minimal area and power consumption.
Data Source
AI summary
A device includes a plurality of input terminals, a control circuit, and a plurality of signal buses. Each of the signal buses is coupled between the control circuit and an associated one of the plurality of input terminals and includes one or more first buffers, one or more second buffers and at least one latch circuit coupled between the one or more first buffers and the one or more second buffers. The one or more first buffers of one of the signal buses are different in number from the one or more first buffers of a different one of the signal buses.