DRAM Bit Line Liner Layer Prevents Barrier Diffusion
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Solution Overview
Problem
During the manufacturing of dynamic random access memory (DRAM), excessive manufacturing temperature alters the lattice of the barrier layer material, leading to short circuits between the bit line and the storage node due to material diffusion through the spacer.
Innovation Solution
A method is implemented where a liner layer is formed on the sidewall of the bit line and barrier layer, using materials like silicon-rich oxide, to prevent lattice alteration and void formation in the spacer, thereby preventing the barrier layer material from passing through and causing short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If excessive manufacturing temperature is used during DRAM fabrication, then the manufacturing process can proceed efficiently, but the lattice of the barrier layer material is altered causing short circuits between the bit line and storage node
Solution Approach 1:
A liner layer is introduced as an intermediary between the barrier layer and the spacer. This liner layer acts as a protective mediator that prevents direct interaction between the barrier layer material and the spacer during high-temperature manufacturing processes, thereby preventing short circuits while maintaining manufacturing efficiency
Solution Approach 2:
The liner layer is formed beforehand on the barrier layer to provide protective cushioning against thermal damage and material diffusion. This prior protective measure prevents lattice alteration and material penetration into the spacer during subsequent high-temperature processing steps
2Ease of manufacture
If the barrier layer material diffuses through the spacer at high temperature, then manufacturing can continue, but short circuits occur between the bit line and storage node
Solution Approach 1:
The liner layer serves as a protective intermediary that maintains clear material boundaries between the barrier layer and spacer. It prevents unwanted material diffusion while allowing the manufacturing process to proceed without interruptions or additional precision control steps
3Device complexity
If no protective layer is added, then the device structure remains simple, but the barrier layer material passes through the spacer causing short circuits
Solution Approach 1:
A thin liner layer is added as a protective intermediary between the barrier layer and spacer. This minimal additional layer provides essential electrical isolation and prevents material diffusion, significantly improving reliability with minimal increase in device complexity
Solution Approach 2:
The structure employs composite material layers where the liner layer (e.g., silicon-rich oxide) is combined with the barrier layer and spacer materials. This composite structure leverages the complementary properties of each material to achieve both electrical isolation and structural integrity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents short circuits between the bit line and storage node by maintaining the integrity of the barrier layer and spacer, ensuring reliable DRAM fabrication.
Implementation Method 1
the liner layer is, for example, fabricated through performing a chemical vapor deposition (CVD) process
Data Source
AI summary
A method of manufacturing a DRAM includes firstly providing a substrate. Many transistors are then formed on the substrate. Next, a first and a second LPCs are formed between the transistors. A first dielectric layer is then formed on the substrate, and a first opening exposing the first LPC is formed in the first dielectric layer. Thereafter, a barrier layer is formed on the first dielectric layer. Afterwards, a BLC is formed in the first opening, and a BL is formed on the first dielectric layer. A liner layer is then formed on a sidewall of the BL. Next, a second dielectric layer having a dry etching rate substantially equal to that of the liner layer and having a wet etching rate larger than that of the liner layer is formed on the substrate. Finally, an SNC is formed in the first and the second dielectric layers.