DRAM Memory Signal Lines for Speed Consistency
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Solution Overview
Problem
In modern DRAM chips, the increased wiring density and reduced size lead to issues such as pressure drop and ground bounce in storage regions away from the bonding pad region, affecting the speed of storage areas far from the bonding pad.
Innovation Solution
The memory design includes multiple storage groups arranged along a first direction, with first signal lines extending along this direction to transmit data to multiple banks and second signal lines arranged correspondingly to each bank, exchanging data through data exchange circuits to reduce transmission distance and improve circuit speed, using metal lines with optimized width and spacing to minimize resistance and coupling capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the bonding pad region is arranged at one side of the wiring region or middle region of storage group, then the wiring density can be increased, but the storage regions away from the bonding pad region experience pressure drop and ground bounce, affecting their speed
Solution Approach 1:
The patent divides the storage group into multiple storage groups arranged along the first direction, with each storage group containing multiple banks. This segmentation allows the introduction of first signal lines that extend along the first direction to serve multiple storage groups, distributing the signal transmission load and reducing the impact of pressure drop and ground bounce on any single region.
Solution Approach 2:
The patent introduces a first direction (extending along the row direction) in addition to the traditional column direction (second direction). First signal lines extend along the first direction to connect multiple storage groups, creating a two-dimensional signal distribution network that reduces transmission distance and improves speed consistency across banks located at different positions.
2Area of stationary object
If signal lines extend long distances from the bonding pad region, then more storage regions can be accessed, but pressure drop and ground bounce increase, reducing circuit speed
Solution Approach 1:
The storage array is segmented into multiple storage groups arranged along the first direction, with each group containing multiple banks. This segmentation enables the use of first signal lines that serve multiple storage groups simultaneously, reducing the effective transmission distance from the bonding pad to any individual bank while maintaining broad coverage.
Solution Approach 2:
First signal lines act as intermediaries that extend along the first direction to connect multiple storage groups. These intermediary signal lines distribute signals more evenly across the memory array, reducing the transmission distance and improving speed for banks located far from the bonding pad region.
3Reliability
If metal lines are used with optimized width and spacing, then resistance and coupling capacitance are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes the physical parameters of metal lines, including width and spacing, to achieve the right balance between electrical performance and manufacturability. By carefully controlling these parameters, the design reduces resistance and coupling capacitance while remaining compatible with standard manufacturing capabilities.
Solution Approach 2:
The patent applies different metal line configurations in different regions. First signal lines extending along the first direction are designed with specific width and spacing optimized for their function of connecting multiple storage groups, while other signal lines use configurations optimized for their local requirements, allowing each region to have the quality needed for its specific function.
Data Source
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AI summary
A memory, comprising: a plurality of storage groups, first signal lines and second signal lines. The plurality of storage groups is arranged along a first direction, each one of the storage groups includes multiple banks, which are arranged along a second direction, and the first direction is perpendicular to the second direction; the first signal lines extend along the first direction, each first signal line is arranged correspondingly to more than one of the multiple banks, and configured to transmit storage data of the more than one of the multiple banks; and the second signal lines extend along the first direction, each one of the second signal lines is arranged correspondingly to a respective bank, and configured to transmit the storage data of the respective bank; wherein the first signal lines exchange the storage data with the second signal lines through respective data exchange circuits.