DRAM Sense Amplifier Reference Voltage Circuit Reduces Current
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Solution Overview
Problem
The existing DRAM cell precharge methods, such as the half VDD precharge and GND precharge, face challenges in maintaining high accuracy in sense amplifier operations due to low power supply voltage and increased current consumption, making it difficult to stabilize the sense amplifier's operation.
Innovation Solution
The semiconductor memory device incorporates a reduced number of transistors for boosting voltage to the gate, utilizing a reference voltage generation circuit and a reference voltage supply switch to precharge bit lines to ground potential, thereby reducing current consumption and stabilizing the sense amplifier's operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the bit line is precharged to GND level using the GND precharge method, then the sense amplifier can operate with higher accuracy, but the current consumption of the voltage-boosting circuit increases
Solution Approach 1:
The patent divides the bit line precharge function into two independent parts: (1) a precharge circuit that charges both bit lines to GND level simultaneously, and (2) a reference voltage supply switch that connects only one bit line to a reference voltage generation circuit. This segmentation allows the sense amplifier to receive proper reference voltage without requiring voltage boosting on all word lines, thus reducing current consumption while maintaining sensing accuracy.
Solution Approach 2:
The patent introduces a reference voltage generation circuit as an intermediary component between the power supply and the bit line. This reference voltage circuit provides a stable voltage level that eliminates the need for voltage-boosting circuits to raise word line potentials, thereby reducing current consumption while enabling accurate sense amplifier operation.
2Reliability
If multiple word lines are raised to potential higher than power source voltage, then the memory cell can be charged/discharged to H level, but the device complexity and current consumption increase
Solution Approach 1:
The patent segments the voltage boosting requirement by applying it only where necessary. Instead of boosting all word lines, only the word line connected to the main memory cell requires voltage boosting for H-level charging, while the reference cell operates with normal voltage levels through the reference voltage supply switch.
Solution Approach 2:
The patent changes the voltage parameter of the reference cell by connecting it to a reference voltage generation circuit that provides an appropriate voltage level without requiring voltage boosting. This parameter change simplifies the overall circuit complexity while maintaining the reliability of memory cell operations.
3Device complexity
If the precharge level is set to half VDD, then the precharge circuit is simpler, but the sense amplifier cannot amplify the potential difference with high accuracy
Solution Approach 1:
The patent introduces a reference voltage supply switch as an intermediary component that connects the reference cell to a reference voltage generation circuit. This reference voltage acts as a mediator that provides the proper voltage level for accurate sense amplifier operation, eliminating the need for complex precharge circuits while maintaining high amplification accuracy.
Solution Approach 2:
The patent changes the precharge voltage parameter from half VDD to GND level, and compensates for this change by introducing a reference voltage generation circuit that provides the appropriate reference level. This parameter change simplifies the precharge circuit while maintaining sense amplifier accuracy through the reference voltage mechanism.
Data Source
AI summary
In one embodiment, a semiconductor memory device includes a plurality of pairs of bit lines, each of said pairs including a first bit line, a second bit line, a memory cell coupled to said first bit line, a sense amplifier determining the logical value stored in the memory cell according to a potential difference between the first and the second bit line, a reference voltage generation circuit, and a reference voltage supply switch coupling an output of the reference voltage generation circuit to the second bit line.