DRAM Refresh Control Circuit Address Comparison
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices require frequent refresh operations to prevent data loss, which can lead to signal interference when performed simultaneously with internal operations in memory blocks sharing a sense amplifier, causing malfunctions.
Innovation Solution
A semiconductor system with a refresh control circuit that generates and compares refresh addresses with active addresses to prevent refresh operations if they correspond to the same or adjacent memory blocks, using a pre-refresh signal generation circuit, address comparison circuit, and refresh signal generation circuit to manage the refresh operation based on these comparisons.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed frequently to prevent data loss in DRAM devices, then data retention reliability is improved, but signal interference and malfunctions occur when refresh operations are performed simultaneously with internal operations in memory blocks sharing a sense amplifier
Solution Approach 1:
The patent introduces an address comparison circuit as an intermediary component that compares refresh addresses with active addresses before executing refresh operations. This mediator prevents direct conflict between refresh and internal operations by detecting address overlaps and generating control signals to block simultaneous operations on shared sense amplifiers, thereby eliminating signal interference while maintaining necessary refresh operations.
Solution Approach 2:
The patent implements a feedback mechanism where the address comparison circuit continuously monitors refresh addresses and active addresses, and based on the comparison result, generates control signals that feedback to the refresh control logic. This feedback loop dynamically adjusts refresh operation timing to avoid conflicts with internal operations, ensuring reliable data retention without causing signal interference.
2Reliability
If refresh operations are performed to maintain data in memory cells, then data integrity is improved, but system complexity increases due to the need for address comparison and control circuits
Solution Approach 1:
The patent merges the address comparison function with the existing refresh control logic by integrating the address comparison circuit into the refresh operation pipeline. The comparison operation is combined with the address generation and decoding processes, allowing the system to perform multiple functions (address generation, comparison, and refresh control) using a unified control structure, thereby reducing overall system complexity.
Solution Approach 2:
The address comparison circuit automatically performs the comparison between refresh addresses and active addresses without requiring external intervention or complex external control logic. The circuit self-generates control signals based on the comparison results, enabling the refresh control mechanism to be self-regulating and reducing the burden on external control systems.
3Productivity
If refresh operations are performed simultaneously with internal operations, then productivity is improved by utilizing memory resources efficiently, but malfunctions occur due to signal interference in shared sense amplifiers
Solution Approach 1:
The patent applies preliminary anti-action by performing address comparison before executing refresh operations. The system proactively identifies potential conflicts between refresh and internal operations by comparing addresses in advance, and generates control signals to prevent simultaneous operations on shared sense amplifiers. This preemptive approach eliminates signal interference before it can occur, ensuring operation stability while allowing non-conflicting parallel operations to proceed.
Data Source
AI summary
A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs an external command and external addresses. The second semiconductor device generates an internal active command in response to the external command, generates active addresses in response to the external addresses, generates a refresh signal and refresh addresses in response to the internal active command, performs an internal operation in response to the internal active command and the active addresses, and performs a refresh operation in response to the refresh signal and the refresh addresses.