DRAM Refresh Control Circuit Variable Cycle Optimization
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Solution Overview
Problem
The uniformity of processing in DRAM devices deteriorates with continuous scaling, leading to manufacturing yield issues and increased power consumption due to uniform refresh cycles applied to all memory cells, which do not account for individual data retention characteristics.
Innovation Solution
A semiconductor memory device with a refresh control circuit, address counter, and address converter that adjusts the number of memory cells refreshed per refresh cycle based on data retention characteristics, allowing for variable refresh operations to optimize the refresh cycle and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a uniform refresh cycle is applied to all memory cells, then the refresh operation is simple to implement, but power consumption increases and manufacturing yield deteriorates due to not accounting for individual data retention characteristics
Solution Approach 1:
The patent applies local quality by assigning different refresh cycle characteristics to different memory cells based on their individual data retention characteristics. Specifically, memory cells are classified into first and second groups with different refresh cycle lengths, allowing each group to be refreshed according to its specific retention needs rather than using a uniform refresh cycle for all cells.
Solution Approach 2:
The patent implements dynamics by making the refresh cycle length variable rather than fixed. The refresh control circuit dynamically adjusts the refresh cycle based on the data retention characteristics of memory cells, transitioning from a static uniform refresh approach to a dynamic adaptive refresh approach that optimizes power consumption while maintaining data integrity.
2Device complexity
If a uniform refresh cycle is applied to all memory cells, then the refresh control is simple, but manufacturing production yield deteriorates due to process scaling variability
Solution Approach 1:
The patent addresses manufacturing yield by applying local quality through differentiated refresh strategies for different memory cell groups. Memory cells exhibiting different data retention characteristics due to process scaling variability are assigned to different refresh groups, allowing each cell to receive appropriate refresh timing tailored to its specific performance characteristics, thereby improving overall production yield.
Solution Approach 2:
The patent applies parameter changes by modifying the refresh cycle length parameter based on observed data retention characteristics. The refresh control circuit changes the refresh cycle parameter from a single uniform value to multiple values corresponding to different memory cell groups, enabling adaptation to process variability and improvement of manufacturing yield.
3Reliability
If the number of memory cells refreshed per refresh control signal is increased, then the refresh coverage is improved, but the refresh cycle length increases and power consumption rises
Solution Approach 1:
The patent applies segmentation by dividing the memory cell array into multiple banks or groups, where each bank can be refreshed independently with different refresh cycle lengths. This allows the system to refresh memory cells with shorter data retention characteristics more frequently while using longer refresh cycles for cells with better retention, thereby maintaining data reliability without unnecessarily extending the overall refresh cycle.
Solution Approach 2:
The patent implements dynamics by enabling the refresh control circuit to dynamically select different refresh cycle lengths for different memory cell groups based on their data retention characteristics. This dynamic approach allows the system to optimize between refresh coverage and cycle length by adapting the refresh strategy to the specific needs of each memory cell group.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, a refresh control circuit, an address counter and an address converter. The memory cell array includes a plurality of memory cells. The refresh control circuit is configured to receive a refresh command and output m refresh control signals during one refresh cycle for refreshing all the memory cells of the semiconductor memory device. The address counter is configured to generate counting signals for refreshing memory cells in response to the m refresh control signals. The address converter is configured to receive the counting signals and output refresh addresses by converting the counting signals in response to a cycle select signal. The address converter is configured to output refresh addresses such that the number of m refresh control signals during one refresh cycle is variable.