DRAM Refresh Control Logic for Access Scenario-Based Timing
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Solution Overview
Problem
Semiconductor memory devices, such as DRAM, face inefficiencies in refresh operations due to the need for external control and timing, which increases system complexity and power consumption, especially when accessed based on specific scenarios like image processing where typical random access is not applicable.
Innovation Solution
A semiconductor memory device with refresh control logic that determines optimal refresh times based on access scenario information and retention characteristics, allowing for self-refresh operations during non-operation periods without external commands, thereby improving refresh efficiency and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DRAM performs refresh operations based on external commands and timing control, then data retention is maintained, but system complexity increases due to additional control components and timing management
Solution Approach 1:
The DRAM device performs self-refresh operations by autonomously determining refresh timing based on access scenario information received from the host. The refresh control logic internally manages refresh operations without requiring external refresh commands or timing control from the host, thereby maintaining data retention while reducing system complexity
Solution Approach 2:
The refresh control functionality is extracted from the host controller and integrated directly into the DRAM device. This transfers the burden of refresh timing management from the host to the DRAM itself, eliminating the need for external refresh command generation and timing control components in the host system
2Reliability
If the DRAM performs refresh operations with external control, then refresh timing can be precisely managed, but power consumption increases due to continuous control signaling
Solution Approach 1:
The DRAM autonomously determines when to perform refresh operations by internally processing access scenario information and calculating appropriate refresh timing based on data retention requirements. This eliminates the need for continuous external control signaling and reduces power consumption associated with host controller operations
Solution Approach 2:
The DRAM performs refresh operations periodically based on calculated refresh intervals derived from access scenario information and retention characteristics. This periodic self-refresh approach replaces continuous external control with efficient periodic internal operations, reducing overall power consumption
3Reliability
If the DRAM uses traditional refresh operations with external commands, then refresh coverage can be ensured, but refresh efficiency decreases due to mandatory timing constraints
Solution Approach 1:
The refresh timing is made dynamic and adaptable to actual access patterns. The refresh control logic calculates optimal refresh timing based on received access scenario information, allowing refresh operations to be performed at the most efficient moments rather than being constrained by fixed external timing schedules
Solution Approach 2:
The refresh operation parameters (timing, frequency, target rows) are dynamically adjusted based on access scenario information and retention characteristics. This allows the system to optimize refresh efficiency for different access patterns while ensuring adequate refresh coverage for data that requires retention
Data Source
AI summary
A semiconductor memory device includes a cell array that includes a plurality of DRAM cells to store data, and refresh control logic that refreshes the plurality of DRAM cells depending on access scenario information provided from an outside. The refresh control logic determines a refresh time of the plurality of DRAM cells with reference to the access scenario information and a retention characteristic of the plurality of DRAM cells and refreshes the plurality of DRAM cells depending on the determined refresh time.