DRAM Refresh Management via Randomized Activate Counter Adjustment
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Solution Overview
Problem
Modern DRAM chips face the 'row hammer' issue where frequent activation and precharge of memory rows can corrupt adjacent rows, especially as feature sizes shrink, and existing mitigation techniques like targeted row refresh are vulnerable to malicious attacks.
Innovation Solution
A memory controller with an activate counter and adjustment circuit that selectively adjusts the refresh command timing by a fixed and varying number, chosen randomly or pseudo-randomly, to mitigate row hammer effects and obscure access patterns from potential attackers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If targeted row refresh (TRR) is used to mitigate row hammer effects, then data corruption from row activation is reduced, but the system becomes vulnerable to malicious attacks that exploit predictable refresh patterns
Solution Approach 1:
The patent implements dynamic refresh interval adjustment where the refresh timing is no longer fixed but varies based on system conditions. The memory controller monitors access patterns and dynamically modifies refresh intervals to prevent attackers from predicting and exploiting refresh timing, thereby maintaining security while ensuring data integrity
Solution Approach 2:
The patent changes the refresh parameter from a static, predictable value to a dynamic, variable value. By introducing variability in refresh timing and making it dependent on monitored system states, the system maintains the protective function against row hammer while eliminating the predictable pattern that malicious attacks exploit
2Reliability
If refresh operations are performed frequently to prevent data corruption, then memory reliability is improved, but system performance deteriorates due to increased interference with normal memory access
Solution Approach 1:
The patent implements dynamic refresh scheduling where refresh operations are performed adaptively based on monitored memory access patterns and system conditions. Instead of fixed frequent refreshes, the system adjusts refresh timing dynamically to perform refreshes only when necessary, thereby maintaining data integrity while minimizing performance impact
Solution Approach 2:
The patent employs feedback mechanisms where the memory controller monitors memory access patterns, row activation frequencies, and system conditions. Based on this feedback, the controller intelligently determines when refresh operations are necessary, optimizing the balance between maintaining data integrity and preserving system performance by avoiding unnecessary refresh operations
Data Source
AI summary
A memory controller interfaces with a dynamic random access memory (DRAM). The memory controller selectively places memory commands in a memory interface queue and transmits the memory commands from the memory interface queue to a memory channel coupled to at least one dynamic random access memory (DRAM). An activate counter is maintained related to a number of activate commands sent over the memory channel to a memory region of the DRAM. In response to the activate counter being at or above a designated threshold, an arbiter is signaled that a refresh command should be sent to the memory region. In response to a designated condition, a value of the activate counter is adjusted by a total number based on a first fixed number and second varying number selected with one of random selection and pseudo-random selection.