DRAM Self-Refresh Interruption for Access Efficiency
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Solution Overview
Problem
Dynamic random access memory (DRAM) systems require frequent refresh operations to maintain data integrity due to charge dissipation in capacitors, leading to inefficiencies and potential data loss during access commands.
Innovation Solution
A DRAM system with a refresh device capable of self-refresh operations that can be interrupted by access commands, allowing for controlled refresh operations to be performed by an external processor, ensuring timely refresh of memory units and reducing data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If self-refresh operation is performed continuously on the memory array, then data integrity is maintained, but access command execution is delayed
Solution Approach 1:
The refresh operation transitions from a static continuous self-refresh mode to a dynamic mode where it can be interrupted by access commands. The refresh device dynamically adjusts its operation based on external interrupts, allowing it to pause self-refresh when access commands are received and resume or perform controlled refresh afterward, thereby resolving the conflict between maintaining data integrity and enabling timely access.
Solution Approach 2:
The system performs preliminary controlled refresh operations on specific refresh units before they are needed for access, based on predicted or scheduled refresh requirements. This allows the memory system to proactively maintain data integrity in high-priority regions without continuously refreshing the entire memory array, reducing the impact on access command execution.
2Reliability
If self-refresh operation completes before access command execution, then data integrity is ensured, but operational efficiency decreases
Solution Approach 1:
The memory array is divided into multiple independent refresh units, each capable of being refreshed independently. This segmentation allows the refresh device to selectively perform controlled refresh operations on specific units that require it, rather than waiting for complete self-refresh cycles of the entire array. Access commands can proceed while other units are being refreshed, improving operational efficiency while maintaining data integrity in accessed units.
Solution Approach 2:
The refresh device acts as an intermediary between the memory array and the external processor, managing refresh operations independently. When access commands are received, the refresh device can interrupt self-refresh and perform controlled refresh on specific units without blocking the access operation, thereby maintaining both data integrity and operational efficiency through coordinated intermediate management.
3Productivity
If access command is executed during self-refresh operation, then operational efficiency improves, but data loss risk increases
Solution Approach 1:
The memory array is segmented into multiple refresh units that can be managed independently. When an access command is received during self-refresh, the system can safely access units that have completed their refresh cycles while deferring or interrupting refresh on other units. This segmentation allows access operations to proceed without causing data loss in accessed units, as those units are either already refreshed or will be refreshed in a controlled manner afterward.
Solution Approach 2:
The refresh device autonomously manages the interruption and resumption of refresh operations based on access command timing. It can identify which refresh units are safe to access and which require deferred refresh, making self-service decisions that minimize data loss risk while maximizing operational efficiency. The system serves itself by automatically coordinating refresh and access operations without external intervention.
Data Source
AI summary
The present disclosure provides a dynamic random access memory (DRAM) and a method of operating the same. The DRAM includes a memory array, a refresh device and an access device. The refresh device is configured to perform a self-refresh operation on the memory array, wherein the self-refresh operation is interrupted in response to an access command. The access device is configured to access the memory array in response to the access command and the interruption of the self-refresh operation.