DRAM Row Fault Detection via Error Parameter Accumulation
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Solution Overview
Problem
The increasing bit errors and decreasing yield of DRAMs due to shrinking fabrication design rules pose challenges in ensuring the reliability and efficiency of semiconductor memory devices.
Innovation Solution
A semiconductor memory device incorporating a memory cell array with error correction code (ECC) engine circuitry, row fault detector circuitry, and control logic circuitry that performs error detection operations, stores error parameters, and determines row faults based on changes in syndrome or column addresses, enabling accurate identification of defective memory cell rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fabrication design rules are shrunk to increase memory density, then memory capacity is improved, but bit error rate increases and yield decreases
Solution Approach 1:
The memory system is segmented into multiple functional components: memory cell array, ECC engine circuitry, row fault detector circuitry, and control logic circuitry. This segmentation allows independent optimization of each component to handle errors introduced by scaled fabrication processes.
Solution Approach 2:
Error detection and fault identification operations are performed preliminarily during memory operations. The ECC engine performs error detection on codewords before data is fully processed, and the row fault detector proactively identifies defective rows, enabling preventive measures to be taken before errors propagate.
2Reliability
If error detection and correction operations are performed on all memory cell rows, then reliability is improved, but operation time increases
Solution Approach 1:
Instead of performing exhaustive error detection on all memory cell rows, the system applies partial action by focusing detection resources on rows that exhibit error patterns. The row fault detector identifies and flags only those rows containing faults, avoiding unnecessary processing of healthy rows and thereby reducing overall operation time while maintaining reliability.
3Reliability
If row fault detection accuracy is improved by analyzing multiple error parameters, then reliability is improved, but device complexity increases
Solution Approach 1:
The row fault detector circuitry is designed with multi-functionality to perform multiple detection tasks using a unified architecture. It can detect various types of row faults (stuck-at faults, bridging faults, coupling faults) using the same basic circuit structure, thereby improving detection accuracy without proportionally increasing device complexity.
Solution Approach 2:
The error detection system utilizes self-service by leveraging the existing ECC engine's error detection capabilities to feed information into the row fault detector. The system uses its own error detection outputs to improve fault identification, eliminating the need for separate external testing equipment or additional complex circuitry.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, row fault detector circuitry and control logic circuitry. The memory cell array includes a plurality of memory cell rows. The control logic circuitry controls the ECC engine circuitry to perform a plurality of error detection operations on each of the memory cell rows. The control logic circuitry controls the row fault detector circuitry to store an error parameter associated with each of a plurality of codewords in each of which at least one error is detected by accumulating the error parameter for each of a plurality of defective memory cell rows. The row fault detector circuitry determines whether a row fault occurs in each of the plurality of defective memory cell rows based on a number of changes of the error parameter.